{ "Info" "ITDB_TH_RESULT" "regl\[1\] d\[1\] clk 2.185 ns register " "Info: th for register \"regl\[1\]\" (data pin = \"d\[1\]\", clock pin = \"clk\") is 2.185 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.542 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 4.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.787 ns) 2.600 ns current_state.st6 3 REG LCFF_X27_Y7_N17 3 " "Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.600 ns; Loc. = LCFF_X27_Y7_N17; Fanout = 3; REG Node = 'current_state.st6'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.489 ns" { clk~clkctrl current_state.st6 } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.631 ns) + CELL(0.000 ns) 3.231 ns current_state.st6~clkctrl 4 COMB CLKCTRL_G4 8 " "Info: 4: + IC(0.631 ns) + CELL(0.000 ns) = 3.231 ns; Loc. = CLKCTRL_G4; Fanout = 8; COMB Node = 'current_state.st6~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.631 ns" { current_state.st6 current_state.st6~clkctrl } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.275 ns) 4.542 ns regl\[1\] 5 REG LCCOMB_X1_Y11_N0 1 " "Info: 5: + IC(1.036 ns) + CELL(0.275 ns) = 4.542 ns; Loc. = LCCOMB_X1_Y11_N0; Fanout = 1; REG Node = 'regl\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.311 ns" { current_state.st6~clkctrl regl[1] } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.051 ns ( 45.16 % ) " "Info: Total cell delay = 2.051 ns ( 45.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.491 ns ( 54.84 % ) " "Info: Total interconnect delay = 2.491 ns ( 54.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.542 ns" { clk clk~clkctrl current_state.st6 current_state.st6~clkctrl regl[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.542 ns" { clk clk~combout clk~clkctrl current_state.st6 current_state.st6~clkctrl regl[1] } { 0.000ns 0.000ns 0.122ns 0.702ns 0.631ns 1.036ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.275ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 24 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.357 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns d\[1\] 1 PIN PIN_21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_21; Fanout = 1; PIN Node = 'd\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { d[1] } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.930 ns) + CELL(0.438 ns) 2.357 ns regl\[1\] 2 REG LCCOMB_X1_Y11_N0 1 " "Info: 2: + IC(0.930 ns) + CELL(0.438 ns) = 2.357 ns; Loc. = LCCOMB_X1_Y11_N0; Fanout = 1; REG Node = 'regl\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.368 ns" { d[1] regl[1] } "NODE_NAME" } } { "ADC0809.vhd" "" { Text "D:/FPGA/ADC0809/ADC0809.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.427 ns ( 60.54 % ) " "Info: Total cell delay = 1.427 ns ( 60.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.930 ns ( 39.46 % ) " "Info: Total interconnect delay = 0.930 ns ( 39.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { d[1] regl[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { d[1] d[1]~combout regl[1] } { 0.000ns 0.000ns 0.930ns } { 0.000ns 0.989ns 0.438ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.542 ns" { clk clk~clkctrl current_state.st6 current_state.st6~clkctrl regl[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.542 ns" { clk clk~combout clk~clkctrl current_state.st6 current_state.st6~clkctrl regl[1] } { 0.000ns 0.000ns 0.122ns 0.702ns 0.631ns 1.036ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.000ns 0.275ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { d[1] regl[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { d[1] d[1]~combout regl[1] } { 0.000ns 0.000ns 0.930ns } { 0.000ns 0.989ns 0.438ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 11 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 26 09:29:44 2007 " "Info: Processing ended: Tue Jun 26 09:29:44 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}