LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY pulse IS
PORT ( clk :IN STD_LOGIC;
          d:IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
       fout:OUT STD_LOGIC;)
END;
ARCHITECTURE one OF pulse IS
SIGNAL full : STD_LOGIC;
BEGIN
p_reg :PROCESS(clk)
VARIABLE cnt8:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF clk'EVENT AND clk ='1'
THEN IF cnt8="11111111" THEN
cnt8:=d;
full<='1';
ELSE cnt8 :=cnt8+1;
full<='0';
END IF;
END IF;
END PROCESS p_reg;
p_div :PROCESS (full)
VARIABLE cnt2:STD_LOGIC;
BEGIN
IF full'EVENT AND full='1' THEN
cnt2:= NOT cnt2;
IF cnt2='1'THEN fout<='1';
ELSE fout <='0';
END IF;
END IF;
END PROCESS p_div;
END;