module transform (clk, rst, sp, Ds, Dp);
inout Ds;
inout [7:0] Dp;
input clk, rst, sp;

reg Dst,sign;
reg [7:0] Dpt;
reg [3:0] counter1, counter2;

assign Ds=sp?1'bz:Dst;
assign Dp=!sp?8'bz:Dpt;  

always @ (posedge clk or negedge rst)
 if(!rst)                   //寄存器初始化
    begin
   Dpt<=0;
   Dst<=0;
   sign<=1;
   counter1<=0;
   counter2<=0;
  end
 else if(sp&&(counter1<=7))//串轉并
  begin
     Dpt[0]<=Ds;           //將串型輸入賦給臨時并型寄存器的最低位
     Dpt[7:1]<=Dpt[6:0];   //臨時并型寄存器的低7位向左移一位。
     counter1<=counter1+1;
    end
 else if(!sp&&sign)         //先于轉換，將并型輸入信號暫存到dpt中，并將sign賦0，以防反復向dpt賦值。
    begin
       Dpt<=Dp;
       sign<=0;
    end
 else if(!sp&&(counter2<=7))//并轉串
    begin         
       Dpt[7:1]<=Dpt[6:0];  //臨時并型寄存器的低7位向左移一位。
       Dst<=Dpt[7];         //把最高位賦給輸出。
       counter2<=counter2+1;
    end   
      
endmodule