---- Project:		AT Atachement interface-- ATA-3 rev7B compliant-- Author:		Richard Herveille-- Version:		1.0 Alpha version Januar 1st, 2001-- rev.: 1.0a Removed all references to records.vhd. Make core compatible with VHDL to Verilog translator tools--            Changed DMA_req signal generation. Make the core compatible with the latest version of the OpenCores DMA engine-- rev.: 1.1  june 18th, 2001. Changed wishbone address-input from ADR_I(4 downto 0) to ADR(6 downto 2)-- rev.: 1.1a june 19th, 2001. Simplified DAT_O output multiplexor---- DeviceType: OCIDEC-3: OpenCores IDE Controller type3-- Features: PIO Compatible Timing, PIO Fast Timing 0/1, Single/Multiword DMA Timing 0/1-- DeviceID: 0x03-- RevNo : 0x00---- Host signals:-- Reset-- DIOR-		read strobe. The falling edge enables data from device onto DD. The rising edge latches data at the host.-- DIOW-		write strobe. The rising edge latches data from DD into the device.-- DMACK-	DMA acknowledge-- DA(2:0)		3bit binary coded adress-- CS0-		select command block registers-- CS1-		select control block registerslibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity atahost is	generic(		TWIDTH : natural := 8;                      -- counter width		-- PIO mode 0 settings (@100MHz clock)		PIO_mode0_T1 : natural := 6;                -- 70ns		PIO_mode0_T2 : natural := 28;               -- 290ns		PIO_mode0_T4 : natural := 2;                -- 30ns		PIO_mode0_Teoc : natural := 23;             -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240		-- Multiword DMA mode 0 settings (@100MHz clock)		DMA_mode0_Tm : natural := 4;                -- 50ns		DMA_mode0_Td : natural := 21;               -- 215ns		DMA_mode0_Teoc : natural := 21              -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215	);	port(		-- WISHBONE SYSCON signals		CLK_I	: in std_logic;		                    	-- master clock in		nReset	: in std_logic := '1';               -- asynchronous active low reset		RST_I : in std_logic := '0';                -- synchronous active high reset		-- WISHBONE SLAVE signals		CYC_I : in std_logic;                       -- valid bus cycle input		STB_I : in std_logic;                       -- strobe/core select input		ACK_O : out std_logic;                      -- strobe acknowledge output		RTY_O : out std_logic;                      -- retry output		ERR_O : out std_logic;                      -- error output		ADR_I : in unsigned(6 downto 2);            -- A6 = '1' ATA devices selected		                                            --          A5 = '1' CS1- asserted, '0' CS0- asserted		                                            --          A4..A2 ATA address lines		                                            -- A6 = '0' ATA controller selected		DAT_I : in std_logic_vector(31 downto 0);   -- Databus in		DAT_O : out std_logic_vector(31 downto 0);  -- Databus out		SEL_I : in std_logic_vector(3 downto 0);    -- Byte select signals		WE_I : in std_logic;                        -- Write enable input		INTA_O : out std_logic;                     -- interrupt request signal IDE0		-- DMA engine signals		DMA_req : out std_logic;                    -- DMA request		DMA_Ack : in std_logic;                     -- DMA acknowledge		-- ATA signals		RESETn	: out std_logic;		DDi	: in std_logic_vector(15 downto 0);		DDo : out std_logic_vector(15 downto 0);		DDoe : out std_logic;		DA	: out unsigned(2 downto 0);		CS0n	: out std_logic;		CS1n	: out std_logic;		DMARQ	: in std_logic;		DMACKn	: out std_logic;		DIORn	: out std_logic;		DIOWn	: out std_logic;		IORDY	: in std_logic;		INTRQ	: in std_logic	);end entity atahost;architecture structural of atahost is	--	-- Device ID	--	constant DeviceId : unsigned(3 downto 0) := x"3";	constant RevisionNo : unsigned(3 downto 0) := x"0";	--	-- component declarations	--	component controller is	generic(		TWIDTH : natural := 8;                   -- counter width		-- PIO mode 0 settings (@100MHz clock)		PIO_mode0_T1 : natural := 6;             -- 70ns		PIO_mode0_T2 : natural := 28;            -- 290ns		PIO_mode0_T4 : natural := 2;             -- 30ns		PIO_mode0_Teoc : natural := 23;          -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240		-- Multiword DMA mode 0 settings (@100MHz clock)		DMA_mode0_Tm : natural := 4;             -- 50ns		DMA_mode0_Td : natural := 21;            -- 215ns		DMA_mode0_Teoc : natural := 21           -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215	);	port(		clk : in std_logic;  		                    	  -- master clock in		nReset	: in std_logic := '1';                 -- asynchronous active low reset		rst : in std_logic := '0';                    -- synchronous active high reset				irq : out std_logic;                          -- interrupt request signal		-- control / registers		IDEctrl_IDEen,		IDEctrl_rst,		IDEctrl_ppen,		IDEctrl_FATR0,		IDEctrl_FATR1 : in std_logic;                 -- control register settings		a : in unsigned(3 downto 0);                  -- address input		d : in std_logic_vector(31 downto 0);         -- data input		we : in std_logic;                            -- write enable input '1'=write, '0'=read		-- PIO registers		PIO_cmdport_T1,		PIO_cmdport_T2,		PIO_cmdport_T4,		PIO_cmdport_Teoc : in unsigned(7 downto 0);		PIO_cmdport_IORDYen : in std_logic;           -- PIO compatible timing settings			PIO_dport0_T1,		PIO_dport0_T2,		PIO_dport0_T4,		PIO_dport0_Teoc : in unsigned(7 downto 0);		PIO_dport0_IORDYen : in std_logic;            -- PIO data-port device0 timing settings		PIO_dport1_T1,		PIO_dport1_T2,		PIO_dport1_T4,		PIO_dport1_Teoc : in unsigned(7 downto 0);		PIO_dport1_IORDYen : in std_logic;            -- PIO data-port device1 timing settings		PIOsel : in std_logic;                        -- PIO controller select		PIOack : out std_logic;                       -- PIO controller acknowledge		PIOq : out std_logic_vector(15 downto 0);     -- PIO data out		PIOtip : buffer std_logic;                    -- PIO transfer in progress		PIOpp_full : out std_logic;                   -- PIO Write PingPong full		-- DMA registers		DMA_dev0_Td,		DMA_dev0_Tm,		DMA_dev0_Teoc : in unsigned(7 downto 0);      -- DMA timing settings for device0		DMA_dev1_Td,		DMA_dev1_Tm,		DMA_dev1_Teoc : in unsigned(7 downto 0);      -- DMA timing settings for device1		DMActrl_DMAen,		DMActrl_dir,		DMActrl_BeLeC0,		DMActrl_BeLeC1 : in std_logic;                -- DMA settings		DMAsel : in std_logic;                        -- DMA controller select		DMAack : out std_logic;                       -- DMA controller acknowledge		DMAq : out std_logic_vector(31 downto 0);     -- DMA data out		DMAtip : buffer std_logic;                    -- DMA transfer in progress		DMA_dmarq : out std_logic;                    -- Synchronized ATA DMARQ line		DMATxFull : buffer std_logic;                 -- DMA transmit buffer full		DMARxEmpty : buffer std_logic;                -- DMA receive buffer empty		DMA_req : out std_logic;                      -- DMA request to external DMA engine		DMA_ack : in std_logic;                       -- DMA acknowledge from external DMA engine		-- ATA signals		RESETn	: out std_logic;		DDi	: in std_logic_vector(15 downto 0);		DDo : out std_logic_vector(15 downto 0);		DDoe : out std_logic;		DA	: out unsigned(2 downto 0);		CS0n	: out std_logic;		CS1n	: out std_logic;		DMARQ	: in std_logic;		DMACKn	: out std_logic;		DIORn	: out std_logic;		DIOWn	: out std_logic;		IORDY	: in std_logic;		INTRQ	: in std_logic	);	end component controller;	-- primary address decoder	signal CONsel, PIOsel, DMAsel : std_logic;        -- controller select, IDE devices select	signal berr, brty : std_logic;                    -- bus error, bus retry	-- registers	-- IDE control register	signal IDEctrl_IDEen, IDEctrl_rst, IDEctrl_ppen, IDEctrl_FATR0, IDEctrl_FATR1 : std_logic;	-- PIO compatible timing settings	signal PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc : unsigned(7 downto 0);	signal PIO_cmdport_IORDYen : std_logic;	-- PIO data register device0 timing settings	signal PIO_dport0_T1, PIO_dport0_T2, PIO_dport0_T4, PIO_dport0_Teoc : unsigned(7 downto 0);	signal PIO_dport0_IORDYen : std_logic;  	-- PIO data register device1 timing settings	signal PIO_dport1_T1, PIO_dport1_T2, PIO_dport1_T4, PIO_dport1_Teoc : unsigned(7 downto 0);	signal PIO_dport1_IORDYen : std_logic;	-- DMA control register	signal DMActrl_DMAen, DMActrl_dir, DMActrl_BeLeC0, DMActrl_BeLeC1 : std_logic;	-- DMA data port device0 timing settings	signal DMA_dev0_Td, DMA_dev0_Tm, DMA_dev0_Teoc : unsigned(7 downto 0);	-- DMA data port device1 timing settings	signal DMA_dev1_Td, DMA_dev1_Tm, DMA_dev1_Teoc : unsigned(7 downto 0);	signal CtrlReg : std_logic_vector(31 downto 0);   -- control register	signal PIOack, DMAack, PIOtip, DMAtip : std_logic;	signal PIOq : std_logic_vector(15 downto 0);	signal PIOpp_full : std_logic;	signal DMAq : std_logic_vector(31 downto 0);	signal DMA_dmarq : std_logic; -- synchronized version of DMARQ	signal DMATxFull, DMARxEmpty : std_logic;	signal stat : std_logic_vector(31 downto 0);	signal irq : std_logic; -- ATA bus IRQ signalbegin	--	-- generate bus cycle / address decoder	--	gen_bc_dec: block		signal w_acc, dw_acc : std_logic;      -- word access, double word access		signal store_pp_full : std_logic;	begin		-- word / double word		w_acc  <= SEL_I(1) and SEL_I(0);		dw_acc <= SEL_I(3) and SEL_I(2) and SEL_I(1) and SEL_I(0);		-- bus error		berr  <= (ADR_I(6) and not w_acc) or (not ADR_I(6) and not dw_acc);		-- bus retry		-- store PIOpp_full, we don't want a PPfull based retry initiated by the current bus-cycle		process(CLK_I)		begin			if (CLK_I'event and CLK_I = '1') then				if (PIOsel = '0') then					store_pp_full <= PIOpp_full;				end if;			end if;