end process;		brty <= (ADR_I(6) and w_acc) and (DMAtip or store_pp_full);	   -- PIO accesses at least 16bit wide, no PIO access during     DMAtip or pingpong full		PIOsel <= CYC_I and STB_I and (ADR_I(6) and w_acc) and not (DMAtip or store_pp_full);		-- CON accesses only 32bit wide		CONsel <= CYC_I and STB_I and (not ADR_I(6) and dw_acc);		DMAsel <= CONsel and ADR_I(5) and ADR_I(4) and ADR_I(3) and ADR_I(2);	end block gen_bc_dec;	--	-- generate registers	--	register_block : block		signal sel_PIO_cmdport, sel_PIO_dport0, sel_PIO_dport1 : std_logic; -- PIO timing registers		signal sel_DMA_dev0, sel_DMA_dev1 : std_logic;                      -- DMA timing registers		signal sel_ctrl, sel_stat : std_logic;                              -- control / status register	begin		-- generate register select signals		sel_ctrl        <= CONsel and WE_I and not ADR_I(5) and not ADR_I(4) and not ADR_I(3) and not ADR_I(2); -- 0x00		sel_stat        <= CONsel and WE_I and not ADR_I(5) and not ADR_I(4) and not ADR_I(3) and     ADR_I(2); -- 0x04		sel_PIO_cmdport <= CONsel and WE_I and not ADR_I(5) and not ADR_I(4) and     ADR_I(3) and not ADR_I(2); -- 0x08		sel_PIO_dport0  <= CONsel and WE_I and not ADR_I(5) and not ADR_I(4) and     ADR_I(3) and     ADR_I(2); -- 0x0C		sel_PIO_dport1  <= CONsel and WE_I and not ADR_I(5) and     ADR_I(4) and not ADR_I(3) and not ADR_I(2); -- 0x10		sel_DMA_dev0    <= CONsel and WE_I and not ADR_I(5) and     ADR_I(4) and not ADR_I(3) and     ADR_I(2); -- 0x14		sel_DMA_dev1    <= CONsel and WE_I and not ADR_I(5) and     ADR_I(4) and     ADR_I(3) and not ADR_I(2); -- 0x18		-- reserved 0x1C-0x38 --		-- reserved 0x3C : DMA port --		-- generate control register		gen_ctrl_reg: process(CLK_I, nRESET)		begin			if (nRESET = '0') then				CtrlReg(31 downto 1) <= (others => '0');				CtrlReg(0)           <= '1';                -- set reset bit			elsif (CLK_I'event and CLK_I = '1') then				if (RST_I = '1') then					CtrlReg(31 downto 1) <= (others => '0');					CtrlReg(0)           <= '1';                -- set reset bit				elsif (sel_ctrl = '1') then					CtrlReg <= DAT_I;				end if;			end if;		end process gen_ctrl_reg;		-- assign bits		DMActrl_DMAen        <= CtrlReg(15);		DMActrl_dir          <= CtrlReg(13);		DMActrl_BeLeC1       <= CtrlReg(9);		DMActrl_BeLeC0       <= CtrlReg(8);		IDEctrl_IDEen        <= CtrlReg(7);		IDEctrl_FATR1        <= CtrlReg(6);		IDEctrl_FATR0        <= CtrlReg(5);		IDEctrl_ppen         <= CtrlReg(4);		PIO_dport1_IORDYen   <= CtrlReg(3);		PIO_dport0_IORDYen   <= CtrlReg(2);		PIO_cmdport_IORDYen  <= CtrlReg(1);		IDEctrl_rst          <= CtrlReg(0);		-- generate status register clearable bits		gen_stat_reg: block			signal dirq, int : std_logic;		begin			gen_irq: process(CLK_I, nRESET)			begin				if (nRESET = '0') then					int <= '0';					dirq <= '0';				elsif (CLK_I'event and CLK_I = '1') then					if (RST_I = '1') then						int <= '0';						dirq <= '0';					else						int <= (int or (irq and not dirq)) and not (sel_stat and not DAT_I(0));						dirq <= irq;					end if;				end if;			end process gen_irq;			gen_stat: process(DMAtip, DMARxEmpty, DMATxFull, DMA_dmarq, PIOtip, int, PIOpp_full)			begin				stat(31 downto 0) <= (others => '0');                -- clear all bits (read unused bits as '0')				stat(31 downto 28) <= std_logic_vector(DeviceId);    -- set Device ID				stat(27 downto 24) <= std_logic_vector(RevisionNo);  -- set revision number				stat(15) <= DMAtip;				stat(10) <= DMARxEmpty;				stat(9)  <= DMATxFull;				stat(8)  <= DMA_dmarq;				stat(7)  <= PIOtip;				stat(6)  <= PIOpp_full;				stat(0)  <= int;			end process;		end block gen_stat_reg;		-- generate PIO compatible / command-port timing register		gen_PIO_cmdport_reg: process(CLK_I, nRESET)		begin			if (nRESET = '0') then				PIO_cmdport_T1   <= conv_unsigned(PIO_mode0_T1, TWIDTH);				PIO_cmdport_T2   <= conv_unsigned(PIO_mode0_T2, TWIDTH);				PIO_cmdport_T4   <= conv_unsigned(PIO_mode0_T4, TWIDTH);				PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, TWIDTH);			elsif (CLK_I'event and CLK_I = '1') then				if (RST_I = '1') then					PIO_cmdport_T1   <= conv_unsigned(PIO_mode0_T1, TWIDTH);					PIO_cmdport_T2   <= conv_unsigned(PIO_mode0_T2, TWIDTH);					PIO_cmdport_T4   <= conv_unsigned(PIO_mode0_T4, TWIDTH);					PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, TWIDTH);				elsif (sel_PIO_cmdport = '1') then					PIO_cmdport_T1   <= unsigned(DAT_I( 7 downto  0));					PIO_cmdport_T2   <= unsigned(DAT_I(15 downto  8));					PIO_cmdport_T4   <= unsigned(DAT_I(23 downto 16));					PIO_cmdport_Teoc <= unsigned(DAT_I(31 downto 24));				end if;			end if;		end process gen_PIO_cmdport_reg;		-- generate PIO device0 timing register		gen_PIO_dport0_reg: process(CLK_I, nRESET)		begin			if (nRESET = '0') then				PIO_dport0_T1   <= conv_unsigned(PIO_mode0_T1, TWIDTH);				PIO_dport0_T2   <= conv_unsigned(PIO_mode0_T2, TWIDTH);				PIO_dport0_T4   <= conv_unsigned(PIO_mode0_T4, TWIDTH);				PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, TWIDTH);			elsif (CLK_I'event and CLK_I = '1') then				if (RST_I = '1') then					PIO_dport0_T1   <= conv_unsigned(PIO_mode0_T1, TWIDTH);					PIO_dport0_T2   <= conv_unsigned(PIO_mode0_T2, TWIDTH);					PIO_dport0_T4   <= conv_unsigned(PIO_mode0_T4, TWIDTH);					PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, TWIDTH);				elsif (sel_PIO_dport0 = '1') then					PIO_dport0_T1   <= unsigned(DAT_I( 7 downto  0));					PIO_dport0_T2   <= unsigned(DAT_I(15 downto  8));					PIO_dport0_T4   <= unsigned(DAT_I(23 downto 16));					PIO_dport0_Teoc <= unsigned(DAT_I(31 downto 24));				end if;			end if;		end process gen_PIO_dport0_reg;		-- generate PIO device1 timing register		gen_PIO_dport1_reg: process(CLK_I, nRESET)		begin			if (nRESET = '0') then				PIO_dport1_T1   <= conv_unsigned(PIO_mode0_T1, TWIDTH);				PIO_dport1_T2   <= conv_unsigned(PIO_mode0_T2, TWIDTH);				PIO_dport1_T4   <= conv_unsigned(PIO_mode0_T4, TWIDTH);				PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, TWIDTH);			elsif (CLK_I'event and CLK_I = '1') then				if (RST_I = '1') then					PIO_dport1_T1   <= conv_unsigned(PIO_mode0_T1, TWIDTH);					PIO_dport1_T2   <= conv_unsigned(PIO_mode0_T2, TWIDTH);					PIO_dport1_T4   <= conv_unsigned(PIO_mode0_T4, TWIDTH);					PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, TWIDTH);				elsif (sel_PIO_dport1 = '1') then					PIO_dport1_T1   <= unsigned(DAT_I( 7 downto  0));					PIO_dport1_T2   <= unsigned(DAT_I(15 downto  8));					PIO_dport1_T4   <= unsigned(DAT_I(23 downto 16));					PIO_dport1_Teoc <= unsigned(DAT_I(31 downto 24));				end if;			end if;		end process gen_PIO_dport1_reg;		-- generate DMA device0 timing register		gen_DMA_dev0_reg: process(CLK_I, nRESET)		begin			if (nRESET = '0') then				DMA_dev0_Tm   <= conv_unsigned(DMA_mode0_Tm, TWIDTH);				DMA_dev0_Td   <= conv_unsigned(DMA_mode0_Td, TWIDTH);				DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, TWIDTH);			elsif (CLK_I'event and CLK_I = '1') then				if (RST_I = '1') then					DMA_dev0_Tm   <= conv_unsigned(DMA_mode0_Tm, TWIDTH);					DMA_dev0_Td   <= conv_unsigned(DMA_mode0_Td, TWIDTH);					DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, TWIDTH);				elsif (sel_DMA_dev0 = '1') then					DMA_dev0_Tm   <= unsigned(DAT_I( 7 downto  0));					DMA_dev0_Td   <= unsigned(DAT_I(15 downto  8));					DMA_dev0_Teoc <= unsigned(DAT_I(31 downto 24));				end if;			end if;		end process gen_DMA_dev0_reg;		-- generate DMA device0 timing register		gen_DMA_dev1_reg: process(CLK_I, nRESET)		begin			if (nRESET = '0') then				DMA_dev1_Tm   <= conv_unsigned(DMA_mode0_Tm, TWIDTH);				DMA_dev1_Td   <= conv_unsigned(DMA_mode0_Td, TWIDTH);				DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, TWIDTH);			elsif (CLK_I'event and CLK_I = '1') then				if (RST_I = '1') then					DMA_dev1_Tm   <= conv_unsigned(DMA_mode0_Tm, TWIDTH);					DMA_dev1_Td   <= conv_unsigned(DMA_mode0_Td, TWIDTH);					DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, TWIDTH);				elsif (sel_DMA_dev1 = '1') then					DMA_dev1_Tm   <= unsigned(DAT_I( 7 downto  0));					DMA_dev1_Td   <= unsigned(DAT_I(15 downto  8));					DMA_dev1_Teoc <= unsigned(DAT_I(31 downto 24));				end if;			end if;		end process gen_DMA_dev1_reg;	end block register_block;	--	-- hookup controller section	--	u1: controller		generic map(TWIDTH => TWIDTH, PIO_mode0_T1 => PIO_mode0_T1, PIO_mode0_T2 => PIO_mode0_T2,	PIO_mode0_T4 => PIO_mode0_T4,			PIO_mode0_Teoc => PIO_mode0_Teoc, DMA_mode0_Tm => DMA_mode0_Tm, DMA_mode0_Td => DMA_mode0_Td, DMA_mode0_Teoc => DMA_mode0_Teoc)		port map(clk => CLK_I, nReset => nRESET, rst => RST_I, irq => irq, IDEctrl_IDEen => IDEctrl_IDEen, IDEctrl_rst => IDEctrl_rst, IDEctrl_ppen => IDEctrl_ppen, 			IDEctrl_FATR0 => IDEctrl_FATR0, IDEctrl_FATR1 => IDEctrl_FATR1,	a => ADR_I(5 downto 2), d => DAT_I, we => WE_I, 			PIO_cmdport_T1 => PIO_cmdport_T1, PIO_cmdport_T2 => PIO_cmdport_T2, PIO_cmdport_T4 => PIO_cmdport_T4, PIO_cmdport_Teoc => PIO_cmdport_Teoc, PIO_cmdport_IORDYen => PIO_cmdport_IORDYen,			PIO_dport0_T1 => PIO_dport0_T1, PIO_dport0_T2 => PIO_dport0_T2, PIO_dport0_T4 => PIO_dport0_T4, PIO_dport0_Teoc => PIO_dport0_Teoc, PIO_dport0_IORDYen => PIO_dport0_IORDYen,			PIO_dport1_T1 => PIO_dport1_T1, PIO_dport1_T2 => PIO_dport1_T2, PIO_dport1_T4 => PIO_dport1_T4, PIO_dport1_Teoc => PIO_dport1_Teoc, PIO_dport1_IORDYen => PIO_dport1_IORDYen,			PIOsel => PIOsel, PIOack => PIOack, PIOq => PIOq, PIOtip => PIOtip, PIOpp_full => PIOpp_full, 			DMActrl_DMAen => DMActrl_DMAen, DMActrl_dir => DMActrl_dir, DMActrl_BeLeC0 => DMActrl_BeLeC0, DMActrl_BeLeC1 => DMActrl_BeLeC1,			DMA_dev0_Td => DMA_dev0_Td, DMA_dev0_Tm => DMA_dev0_Tm, DMA_dev0_Teoc => DMA_dev0_Teoc,			DMA_dev1_Td => DMA_dev1_Td, DMA_dev1_Tm => DMA_dev1_Tm, DMA_dev1_Teoc => DMA_dev1_Teoc,			DMAsel => DMAsel, DMAack => DMAack, DMAq => DMAq, DMAtip => DMAtip, DMA_dmarq => DMA_dmarq, DMATxFull => DMATxFull, 			DMARxEmpty => DMARxEmpty, DMA_req => DMA_req, DMA_ack => DMA_ack, RESETn => RESETn, DDi => DDi, DDo => DDo, DDoe => DDoe, 			DA => DA, CS0n	=> CS0n, CS1n => CS1n, DMARQ => DMARQ, DMACKn => DMACKn, DIORn => DIORn, DIOWn => DIOWn, IORDY => IORDY, INTRQ	=> INTRQ);	--	-- generate WISHBONE interconnect signals	--	gen_WB_sigs: block		signal Q : std_logic_vector(31 downto 0);	begin		-- generate acknowledge signal		ACK_O <= PIOack or CONsel; -- or DMAack; -- since DMAack is derived from CONsel this is OK		-- generate error signal		ERR_O <= CYC_I and STB_I and berr;		-- generate retry signal		RTY_O <= CYC_I and STB_I and brty;		-- assign interrupt signal		INTA_O <= stat(0);			-- generate output multiplexor		with ADR_I(5 downto 2) select			Q <= CtrlReg when "0000", -- control register			     stat    when "0001", -- status register			     std_logic_vector(PIO_cmdport_Teoc & PIO_cmdport_T4 & PIO_cmdport_T2 & PIO_cmdport_T1) when "0010", -- PIO compatible / cmd-port timing register			     std_logic_vector(PIO_dport0_Teoc & PIO_dport0_T4 & PIO_dport0_T2 & PIO_dport0_T1)     when "0011", -- PIO fast timing register device0			     std_logic_vector(PIO_dport1_Teoc & PIO_dport1_T4 & PIO_dport1_T2 & PIO_dport1_T1)     when "0100", -- PIO fast timing register device1			     std_logic_vector(DMA_dev0_Teoc & x"00" & DMA_dev0_Td & DMA_dev0_Tm)                   when "0101", -- DMA timing register device0			     std_logic_vector(DMA_dev1_Teoc & x"00" & DMA_dev1_Td & DMA_dev1_Tm)                   when "0110", -- DMA timing register device1			     DMAq    when "1111", -- DMA port, DMA receive register		       (others => '0') when others;		DAT_O <= (x"0000" & PIOq) when (ADR_I(6) = '1') else Q;	end block gen_WB_sigs;end architecture structural;