?? mt46v16m16.vhd
字號:
-----------------------------------------------------------------------------------------
--
-- File Name: MT46V16M16.VHD
-- Version: 2.1
-- Date: January 14th, 2002
-- Model: Behavioral
-- Simulator: NCDesktop - http://www.cadence.com
-- ModelSim PE - http://www.model.com
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: sphuynh@micron.com
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks)
--
-- Description: Micron 256 Mb SDRAM DDR (Double Data Rate)
--
-- Limitation: Doesn't model internal refresh counter
--
-- Note:
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Date Changes
-- --- ---------------------------- ---------- -------------------------------------
-- 2.1 Son P. Huynh 01/14/2002 - Fix Burst_counter
-- Micron Technology, Inc.
--
-- 2.0 Son P. Huynh 11/08/2001 - Second release
-- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE
--
-----------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY MT46V16M16 IS
GENERIC ( -- Timing for -75Z CL2
tCK : TIME := 7.500 ns;
tCH : TIME := 3.375 ns; -- 0.45*tCK
tCL : TIME := 3.375 ns; -- 0.45*tCK
tDH : TIME := 0.500 ns;
tDS : TIME := 0.500 ns;
tIH : TIME := 0.900 ns;
tIS : TIME := 0.900 ns;
tMRD : TIME := 15.000 ns;
tRAS : TIME := 40.000 ns;
tRAP : TIME := 20.000 ns;
tRC : TIME := 65.000 ns;
tRFC : TIME := 75.000 ns;
tRCD : TIME := 20.000 ns;
tRP : TIME := 20.000 ns;
tRRD : TIME := 15.000 ns;
tWR : TIME := 15.000 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
cols_bits : INTEGER := 9
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Clk : IN STD_LOGIC;
Clk_n : IN STD_LOGIC;
Cke : IN STD_LOGIC;
Cs_n : IN STD_LOGIC;
Ras_n : IN STD_LOGIC;
Cas_n : IN STD_LOGIC;
We_n : IN STD_LOGIC;
Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END MT46V16M16;
ARCHITECTURE behave OF MT46V16M16 IS
-- Array for Read pipeline
TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-- Array for Write pipeline
TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-- Array for Auto Precharge
TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER;
-- Array for Manual Precharge
TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0);
TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-- Array for Burst Terminate
TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC;
-- Array for Memory Access
TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
TYPE Array_ram_pntr IS ACCESS Array_ram_type;
TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr;
-- Data pair
SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0);
SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0);
-- Mode Register
SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
-- Command Decode Variables
SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0';
-- Burst Length Decode Variables
SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0';
-- Cas Latency Decode Variables
SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0';
-- Internal Control Signals
SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0';
-- System Clock
SIGNAL Sys_clk : STD_LOGIC := '0';
-- Dqs buffer
SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ";
BEGIN
-- Strip the strength
Cs_in <= To_X01 (Cs_n);
Ras_in <= To_X01 (Ras_n);
Cas_in <= To_X01 (Cas_n);
We_in <= To_X01 (We_n);
-- Commands Decode
Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in);
Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1));
Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1));
Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4));
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4));
-- Dqs buffer
Dqs <= Dqs_out;
--
-- System Clock
--
int_clk : PROCESS (Clk, Clk_n)
VARIABLE ClkZ, CkeZ : STD_LOGIC := '0';
begin
IF Clk = '1' AND Clk_n = '0' THEN
ClkZ := '1';
CkeZ := Cke;
ELSIF Clk = '0' AND Clk_n = '1' THEN
ClkZ := '0';
END IF;
Sys_clk <= CkeZ AND ClkZ;
END PROCESS;
--
-- Main Process
--
state_register : PROCESS
-- Precharge Variables
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0';
-- Activate Variables
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1';
-- Data IO variables
VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0';
-- Internal address mux variables
VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0);
VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
-- DLL Reset variables
VARIABLE DLL_enable : STD_LOGIC := '0';
VARIABLE DLL_reset : STD_LOGIC := '0';
VARIABLE DLL_done : STD_LOGIC := '0';
VARIABLE DLL_count : INTEGER := 0;
-- Timing Check
VARIABLE MRD_chk : TIME := 0 ns;
VARIABLE RFC_chk : TIME := 0 ns;
VARIABLE RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns;
VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns;
-- Read pipeline variables
VARIABLE Read_cmnd : Array_Read_cmnd;
VARIABLE Read_bank : Array_Read_bank;
VARIABLE Read_cols : Array_Read_cols;
-- Write pipeline variables
VARIABLE Write_cmnd : Array_Write_cmnd;
VARIABLE Write_bank : Array_Write_bank;
VARIABLE Write_cols : Array_Write_cols;
-- Auto Precharge variables
VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0');
VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 );
-- Manual Precharge variables
VARIABLE A10_precharge : Array_A10_precharge;
VARIABLE Bank_precharge : Array_Bank_precharge;
VARIABLE Cmnd_precharge : Array_Cmnd_precharge;
-- Burst Terminate variable
VARIABLE Cmnd_bst : Array_Cmnd_bst;
-- Memory Banks
VARIABLE Bank0 : Array_ram_stor;
VARIABLE Bank1 : Array_ram_stor;
VARIABLE Bank2 : Array_ram_stor;
VARIABLE Bank3 : Array_ram_stor;
-- Burst Counter
VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0);
-- Internal Dqs initialize
VARIABLE Dqs_int : STD_LOGIC := '0';
-- Data buffer for DM Mask
VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
--
-- Initialize empty rows
--
PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW Array_ram_type;
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
Bank2 (Row_index) := NEW Array_ram_type;
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank2 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "11" THEN
IF Bank3 (Row_index) = NULL THEN
Bank3 (Row_index) := NEW Array_ram_type;
FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank3 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
--
-- Burst Counter
--
PROCEDURE Burst_decode IS
VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance burst counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Cols_temp := Cols_addr + 1;
ELSIF Mode_reg (3) = '1' THEN
Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2);
Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1);
Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
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