`timescale 1ns / 1ps////////////////////////////////////////////////////////////////////////////////// Company: // Engineer://// Create Date:   22:37:19 10/29/2007// Design Name:   clk_div// Module Name:   G:/Xilinx/ISEexamples/mcu1/clk_div_tb.v// Project Name:  mcu1// Target Device:  // Tool versions:  // Description: //// Verilog Test Fixture created by ISE for module: clk_div//// Dependencies:// // Revision:// Revision 0.01 - File Created// Additional Comments:// ////////////////////////////////////////////////////////////////////////////////module clk_div_tb_v;	// Inputs	reg clkin;	// Outputs	wire clk1;	wire clk2;	wire clk3;	// Instantiate the Unit Under Test (UUT)	clk_div uut (		.clkin(clkin), 		.clk1(clk1), 		.clk2(clk2), 		.clk3(clk3)	);	initial begin		// Initialize Inputs
		#100; 		clkin = 0;				// Wait 100 ns for global reset to finish				forever		#100 clkin = ~clkin;        		// Add stimulus here	end      endmodule