library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity timec is
port(
seca:in std_logic_vector(7 downto 0);
secb:in std_logic_vector(7 downto 0);
mina:in std_logic_vector(7 downto 0);
minb:in std_logic_vector(7 downto 0);
hra:in std_logic_vector(7 downto 0);
hrb:in std_logic_vector(7 downto 0);
sel:in std_logic_vector(2 downto 0);
q:out std_logic_vector(7 downto 0));
end timec;

architecture a of timec is
begin
process(sel,seca,secb,mina,minb,hra,hrb)
begin
case sel is
when "000"=>q<="1"&seca(6 downto 0 );
when "001"=>q<=secb;
when "010"=>q<="1"&mina(6 downto 0 );
when "011"=>q<=minb;
when "100"=>q<="1"&hra(6 downto 0 );
when "101"=>q<=hrb;
when others=>q<="00000000";
end case;
end process;
end a ;