library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity divclk is
port (clk : in std_logic;
      clk1 : out std_logic;
      clk2 : out std_logic;
      clk3 : out std_logic;
      clk4 : out std_logic);
constant number1:integer:=1000;
constant number2:integer:=250;
constant number3:integer:=50;
end;
architecture a of divclk is
signal temp1: std_logic;
signal temp2: std_logic;
signal temp3: std_logic;
signal temp4: std_logic;
begin
clk4<=temp4;
clk3<=temp3;
clk2<=temp2;
clk1<=temp1;
process(clk)
variable counter1: integer range 0 to 8191;
variable counter2: integer range 0 to 8191;
variable counter3: integer range 0 to 8191;

begin
if(clk'event and clk='1') then
counter1:=counter1+1;
counter2:=counter2+1;
counter3:=counter3+1;
if (counter1=number1) then temp1<='1';counter1:=0;else temp1<='0';
end if; 
if (counter2=number2) then temp2<='1';counter2:=0;else temp2<='0';
end if; 
if (counter3=number3) then temp3<='1';counter3:=0;else temp3<='0'; 
end if;
end if;
temp4<=clk;
end process;
end;