library ieee;
use ieee.std_logic_1164.all;

entity deco10 is 
port(sel :in std_logic_vector(3 downto 0);
disable:in std_logic;
q:out std_logic_vector(7 downto 0));
end deco10;

architecture a of deco10 is
signal tq:std_logic_vector(7 downto 0);
begin
with sel select
tq<="00111111" when "0000",
    "00000110" when "0001",
    "01011011" when "0010",
    "01001111" when "0011",
    "01100110" when "0100",
    "01101101" when "0101",
    "01111101" when "0110",
    "00100111" when "0111",
    "01111111" when "1000",
    "01101111" when "1001",
    "00000000" when others;
q<=tq when disable='0' else "00000000";
end a;