?? shift_reg_pa.v
字號:
// Note: This model corrects the model on p. 159
module shiftreg_PA (E, A, clk, rst);
output A;
input E;
input clk, rst;
reg A, B, C, D;
always @ (posedge clk or posedge rst) begin
if (reset) begin A = 0; B = 0; C = 0; D = 0; end
else begin
A = B;
B = C;
C = D;
D = E;
end
end
endmodule
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