?? fft.map.eqn

?? 關于FFT實現的Verilog代碼
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--F2_result[7] is lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[7]
--operation mode is normal

F2_result[7]_carry_eqn = F2L51;
F2_result[7] = F6_result[13] $ x1_im[7] $ !F2_result[7]_carry_eqn;


--F2_result[6] is lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[6]
--operation mode is arithmetic

F2_result[6]_carry_eqn = F2L31;
F2_result[6] = F6_result[12] $ x1_im[6] $ F2_result[6]_carry_eqn;

--F2L51 is lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[6]~COUT
--operation mode is arithmetic

F2L51 = CARRY(F6_result[12] & x1_im[6] & !F2L31 # !F6_result[12] & (x1_im[6] # !F2L31));


--F2_result[5] is lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[5]
--operation mode is arithmetic

F2_result[5]_carry_eqn = F2L11;
F2_result[5] = F6_result[11] $ x1_im[5] $ !F2_result[5]_carry_eqn;

--F2L31 is lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[5]~COUT
--operation mode is arithmetic

F2L31 = CARRY(F6_result[11] & (!F2L11 # !x1_im[5]) # !F6_result[11] & !x1_im[5] & !F2L11);


--F2_result[4] is lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[4]
--operation mode is arithmetic

F2_result[4]_carry_eqn = F2L9;
F2_result[4] = F6_result[10] $ x1_im[4] $ F2_result[4]_carry_eqn;

--F2L11 is lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT
--operation mode is arithmetic

F2L11 = CARRY(F6_result[10] & x1_im[4] & !F2L9 # !F6_result[10] & (x1_im[4] # !F2L9));


--F2_result[3] is lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[3]
--operation mode is arithmetic

F2_result[3]_carry_eqn = F2L7;
F2_result[3] = F6_result[9] $ x1_im[3] $ !F2_result[3]_carry_eqn;

--F2L9 is lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT
--operation mode is arithmetic

F2L9 = CARRY(F6_result[9] & (!F2L7 # !x1_im[3]) # !F6_result[9] & !x1_im[3] & !F2L7);


--F2_result[2] is lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[2]
--operation mode is arithmetic

F2_result[2]_carry_eqn = F2L5;
F2_result[2] = F6_result[8] $ x1_im[2] $ F2_result[2]_carry_eqn;

--F2L7 is lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT
--operation mode is arithmetic

F2L7 = CARRY(F6_result[8] & x1_im[2] & !F2L5 # !F6_result[8] & (x1_im[2] # !F2L5));


--F2_result[1] is lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[1]
--operation mode is arithmetic

F2_result[1]_carry_eqn = F2L3;
F2_result[1] = F6_result[7] $ x1_im[1] $ !F2_result[1]_carry_eqn;

--F2L5 is lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[1]~COUT
--operation mode is arithmetic

F2L5 = CARRY(F6_result[7] & (!F2L3 # !x1_im[1]) # !F6_result[7] & !x1_im[1] & !F2L3);


--F2_result[0] is lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[0]
--operation mode is arithmetic

F2_result[0] = F6_result[6] $ x1_im[0];

--F2L3 is lpm_add_sua:add_x1_x2_im1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[0]~COUT
--operation mode is arithmetic

F2L3 = CARRY(x1_im[0] # !F6_result[6]);


--F1_result[7] is lpm_add_sua:add_x1_x2_im|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[7]
--operation mode is normal

F1_result[7]_carry_eqn = F1L51;
F1_result[7] = F6_result[13] $ x1_im[7] $ F1_result[7]_carry_eqn;


--F1_result[6] is lpm_add_sua:add_x1_x2_im|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[6]
--operation mode is arithmetic

F1_result[6]_carry_eqn = F1L31;
F1_result[6] = F6_result[12] $ x1_im[6] $ !F1_result[6]_carry_eqn;

--F1L51 is lpm_add_sua:add_x1_x2_im|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[6]~COUT
--operation mode is arithmetic

F1L51 = CARRY(F6_result[12] & (x1_im[6] # !F1L31) # !F6_result[12] & x1_im[6] & !F1L31);


--F1_result[5] is lpm_add_sua:add_x1_x2_im|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[5]
--operation mode is arithmetic

F1_result[5]_carry_eqn = F1L11;
F1_result[5] = F6_result[11] $ x1_im[5] $ F1_result[5]_carry_eqn;

--F1L31 is lpm_add_sua:add_x1_x2_im|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[5]~COUT
--operation mode is arithmetic

F1L31 = CARRY(F6_result[11] & !x1_im[5] & !F1L11 # !F6_result[11] & (!F1L11 # !x1_im[5]));


--F1_result[4] is lpm_add_sua:add_x1_x2_im|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[4]
--operation mode is arithmetic

F1_result[4]_carry_eqn = F1L9;
F1_result[4] = F6_result[10] $ x1_im[4] $ !F1_result[4]_carry_eqn;

--F1L11 is lpm_add_sua:add_x1_x2_im|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT
--operation mode is arithmetic

F1L11 = CARRY(F6_result[10] & (x1_im[4] # !F1L9) # !F6_result[10] & x1_im[4] & !F1L9);


--F1_result[3] is lpm_add_sua:add_x1_x2_im|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[3]
--operation mode is arithmetic

F1_result[3]_carry_eqn = F1L7;
F1_result[3] = F6_result[9] $ x1_im[3] $ F1_result[3]_carry_eqn;

--F1L9 is lpm_add_sua:add_x1_x2_im|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT
--operation mode is arithmetic

F1L9 = CARRY(F6_result[9] & !x1_im[3] & !F1L7 # !F6_result[9] & (!F1L7 # !x1_im[3]));


--F1_result[2] is lpm_add_sua:add_x1_x2_im|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[2]
--operation mode is arithmetic

F1_result[2]_carry_eqn = F1L5;
F1_result[2] = F6_result[8] $ x1_im[2] $ !F1_result[2]_carry_eqn;

--F1L7 is lpm_add_sua:add_x1_x2_im|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT
--operation mode is arithmetic

F1L7 = CARRY(F6_result[8] & (x1_im[2] # !F1L5) # !F6_result[8] & x1_im[2] & !F1L5);


--F1_result[1] is lpm_add_sua:add_x1_x2_im|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[1]
--operation mode is arithmetic

F1_result[1]_carry_eqn = F1L3;
F1_result[1] = F6_result[7] $ x1_im[1] $ F1_result[1]_carry_eqn;

--F1L5 is lpm_add_sua:add_x1_x2_im|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[1]~COUT
--operation mode is arithmetic

F1L5 = CARRY(F6_result[7] & !x1_im[1] & !F1L3 # !F6_result[7] & (!F1L3 # !x1_im[1]));


--F1_result[0] is lpm_add_sua:add_x1_x2_im|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[0]
--operation mode is arithmetic

F1_result[0] = F6_result[6] $ x1_im[0];

--F1L3 is lpm_add_sua:add_x1_x2_im|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[0]~COUT
--operation mode is arithmetic

F1L3 = CARRY(F6_result[6] & x1_im[0]);


--F4_result[7] is lpm_add_sua:add_x1_x2_re1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[7]
--operation mode is normal

F4_result[7]_carry_eqn = F4L51;
F4_result[7] = F5_result[13] $ x1_re[7] $ !F4_result[7]_carry_eqn;


--F4_result[6] is lpm_add_sua:add_x1_x2_re1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[6]
--operation mode is arithmetic

F4_result[6]_carry_eqn = F4L31;
F4_result[6] = F5_result[12] $ x1_re[6] $ F4_result[6]_carry_eqn;

--F4L51 is lpm_add_sua:add_x1_x2_re1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[6]~COUT
--operation mode is arithmetic

F4L51 = CARRY(F5_result[12] & x1_re[6] & !F4L31 # !F5_result[12] & (x1_re[6] # !F4L31));


--F4_result[5] is lpm_add_sua:add_x1_x2_re1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[5]
--operation mode is arithmetic

F4_result[5]_carry_eqn = F4L11;
F4_result[5] = F5_result[11] $ x1_re[5] $ !F4_result[5]_carry_eqn;

--F4L31 is lpm_add_sua:add_x1_x2_re1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[5]~COUT
--operation mode is arithmetic

F4L31 = CARRY(F5_result[11] & (!F4L11 # !x1_re[5]) # !F5_result[11] & !x1_re[5] & !F4L11);


--F4_result[4] is lpm_add_sua:add_x1_x2_re1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[4]
--operation mode is arithmetic

F4_result[4]_carry_eqn = F4L9;
F4_result[4] = F5_result[10] $ x1_re[4] $ F4_result[4]_carry_eqn;

--F4L11 is lpm_add_sua:add_x1_x2_re1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT
--operation mode is arithmetic

F4L11 = CARRY(F5_result[10] & x1_re[4] & !F4L9 # !F5_result[10] & (x1_re[4] # !F4L9));


--F4_result[3] is lpm_add_sua:add_x1_x2_re1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[3]
--operation mode is arithmetic

F4_result[3]_carry_eqn = F4L7;
F4_result[3] = F5_result[9] $ x1_re[3] $ !F4_result[3]_carry_eqn;

--F4L9 is lpm_add_sua:add_x1_x2_re1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT
--operation mode is arithmetic

F4L9 = CARRY(F5_result[9] & (!F4L7 # !x1_re[3]) # !F5_result[9] & !x1_re[3] & !F4L7);


--F4_result[2] is lpm_add_sua:add_x1_x2_re1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[2]
--operation mode is arithmetic

F4_result[2]_carry_eqn = F4L5;
F4_result[2] = F5_result[8] $ x1_re[2] $ F4_result[2]_carry_eqn;

--F4L7 is lpm_add_sua:add_x1_x2_re1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT
--operation mode is arithmetic

F4L7 = CARRY(F5_result[8] & x1_re[2] & !F4L5 # !F5_result[8] & (x1_re[2] # !F4L5));


--F4_result[1] is lpm_add_sua:add_x1_x2_re1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[1]
--operation mode is arithmetic

F4_result[1]_carry_eqn = F4L3;
F4_result[1] = F5_result[7] $ x1_re[1] $ !F4_result[1]_carry_eqn;

--F4L5 is lpm_add_sua:add_x1_x2_re1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[1]~COUT
--operation mode is arithmetic

F4L5 = CARRY(F5_result[7] & (!F4L3 # !x1_re[1]) # !F5_result[7] & !x1_re[1] & !F4L3);


--F4_result[0] is lpm_add_sua:add_x1_x2_re1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[0]
--operation mode is arithmetic

F4_result[0] = F5_result[6] $ x1_re[0];

--F4L3 is lpm_add_sua:add_x1_x2_re1|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[0]~COUT
--operation mode is arithmetic

F4L3 = CARRY(x1_re[0] # !F5_result[6]);


--F3_result[7] is lpm_add_sua:add_x1_x2_re|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[7]
--operation mode is normal

F3_result[7]_carry_eqn = F3L51;
F3_result[7] = F5_result[13] $ x1_re[7] $ F3_result[7]_carry_eqn;


--F3_result[6] is lpm_add_sua:add_x1_x2_re|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[6]
--operation mode is arithmetic

F3_result[6]_carry_eqn = F3L31;
F3_result[6] = F5_result[12] $ x1_re[6] $ !F3_result[6]_carry_eqn;

--F3L51 is lpm_add_sua:add_x1_x2_re|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[6]~COUT
--operation mode is arithmetic

F3L51 = CARRY(F5_result[12] & (x1_re[6] # !F3L31) # !F5_result[12] & x1_re[6] & !F3L31);


--F3_result[5] is lpm_add_sua:add_x1_x2_re|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[5]
--operation mode is arithmetic

F3_result[5]_carry_eqn = F3L11;
F3_result[5] = F5_result[11] $ x1_re[5] $ F3_result[5]_carry_eqn;

--F3L31 is lpm_add_sua:add_x1_x2_re|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[5]~COUT
--operation mode is arithmetic

F3L31 = CARRY(F5_result[11] & !x1_re[5] & !F3L11 # !F5_result[11] & (!F3L11 # !x1_re[5]));


--F3_result[4] is lpm_add_sua:add_x1_x2_re|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[4]
--operation mode is arithmetic

F3_result[4]_carry_eqn = F3L9;
F3_result[4] = F5_result[10] $ x1_re[4] $ !F3_result[4]_carry_eqn;

--F3L11 is lpm_add_sua:add_x1_x2_re|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT
--operation mode is arithmetic

F3L11 = CARRY(F5_result[10] & (x1_re[4] # !F3L9) # !F5_result[10] & x1_re[4] & !F3L9);


--F3_result[3] is lpm_add_sua:add_x1_x2_re|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[3]
--operation mode is arithmetic

F3_result[3]_carry_eqn = F3L7;
F3_result[3] = F5_result[9] $ x1_re[3] $ F3_result[3]_carry_eqn;

--F3L9 is lpm_add_sua:add_x1_x2_re|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT
--operation mode is arithmetic

F3L9 = CARRY(F5_result[9] & !x1_re[3] & !F3L7 # !F5_result[9] & (!F3L7 # !x1_re[3]));


--F3_result[2] is lpm_add_sua:add_x1_x2_re|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[2]
--operation mode is arithmetic

F3_result[2]_carry_eqn = F3L5;
F3_result[2] = F5_result[8] $ x1_re[2] $ !F3_result[2]_carry_eqn;

--F3L7 is lpm_add_sua:add_x1_x2_re|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT
--operation mode is arithmetic

F3L7 = CARRY(F5_result[8] & (x1_re[2] # !F3L5) # !F5_result[8] & x1_re[2] & !F3L5);


--F3_result[1] is lpm_add_sua:add_x1_x2_re|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[1]
--operation mode is arithmetic

F3_result[1]_carry_eqn = F3L3;
F3_result[1] = F5_result[7] $ x1_re[1] $ F3_result[1]_carry_eqn;

--F3L5 is lpm_add_sua:add_x1_x2_re|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[1]~COUT
--operation mode is arithmetic

F3L5 = CARRY(F5_result[7] & !x1_re[1] & !F3L3 # !F5_result[7] & (!F3L3 # !x1_re[1]));


--F3_result[0] is lpm_add_sua:add_x1_x2_re|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[0]
--operation mode is arithmetic

F3_result[0] = F5_result[6] $ x1_re[0];

--F3L3 is lpm_add_sua:add_x1_x2_re|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[0]~COUT
--operation mode is arithmetic

F3L3 = CARRY(F5_result[6] & x1_re[0]);


--F6_result[15] is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[15]
--operation mode is normal

F6_result[15]_carry_eqn = F6L13;
F6_result[15] = H2_result[15] $ H4_result[15] $ F6_result[15]_carry_eqn;


--F6_result[14] is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[14]
--operation mode is arithmetic

F6_result[14]_carry_eqn = F6L92;
F6_result[14] = H2_result[14] $ H4_result[14] $ !F6_result[14]_carry_eqn;

--F6L13 is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[14]~COUT
--operation mode is arithmetic

F6L13 = CARRY(H2_result[14] & (H4_result[14] # !F6L92) # !H2_result[14] & H4_result[14] & !F6L92);


--F6_result[13] is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[13]
--operation mode is arithmetic

F6_result[13]_carry_eqn = F6L72;
F6_result[13] = H2_result[13] $ H4_result[13] $ F6_result[13]_carry_eqn;

--F6L92 is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[13]~COUT
--operation mode is arithmetic

F6L92 = CARRY(H2_result[13] & !H4_result[13] & !F6L72 # !H2_result[13] & (!F6L72 # !H4_result[13]));


--F6_result[12] is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[12]
--operation mode is arithmetic

F6_result[12]_carry_eqn = F6L52;
F6_result[12] = H2_result[12] $ H4_result[12] $ !F6_result[12]_carry_eqn;

--F6L72 is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[12]~COUT
--operation mode is arithmetic

F6L72 = CARRY(H2_result[12] & (H4_result[12] # !F6L52) # !H2_result[12] & H4_result[12] & !F6L52);


--F6_result[11] is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[11]
--operation mode is arithmetic

F6_result[11]_carry_eqn = F6L32;
F6_result[11] = H2_result[11] $ H4_result[11] $ F6_result[11]_carry_eqn;

--F6L52 is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|add_sub_cell[11]~COUT
--operation mode is arithmetic

F6L52 = CARRY(H2_result[11] & !H4_result[11] & !F6L32 # !H2_result[11] & (!F6L32 # !H4_result[11]));


--F6_result[10] is lpm_add_sub_16:out3_out4|lpm_add_sub:lpm_add_sub_component|alt_stratix_add_sub:stratix_adder|result[10]
--operation mode is arithmetic

F6_result[10]_carry_eqn = F6L12;
F6_result[10] = H2_result[10] $ H4_result[10] $ !F6_result[10]_carry_eqn;
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?? 文件大小 402 K
?? 上傳用戶 liyueyuan2011
?? 所屬分類 VHDL/FPGA/Verilog
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