# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = TrueSET verilogsim = TrueSET workingdirectory = E:\work\gphy_vhdlSET speedgrade = -4SET simulationfiles = BehavioralSET asysymbol = TrueSET addpads = FalseSET device = xc3s1500SET implementationfiletype = EdifSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = fg676SET createndf = FalseSET designentry = VHDLSET devicefamily = spartan3SET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Asynchronous_FIFO family Xilinx,_Inc. 6.1# END Select# BEGIN ParametersCSET create_rpm=falseCSET read_acknowledge=falseCSET almost_empty_flag=falseCSET write_acknowledge=falseCSET memory_type=blockCSET read_acknowledge_sense=active_highCSET read_count_width=2CSET fifo_depth=511CSET component_name=infifoCSET write_count_width=2CSET write_count=falseCSET read_count=falseCSET write_error=falseCSET read_error=falseCSET read_error_sense=active_highCSET almost_full_flag=falseCSET write_acknowledge_sense=active_highCSET write_error_sense=active_highCSET input_data_width=8# END ParametersGENERATE