?? para_mach_d.v
字號(hào):
`timescale 1 ns / 100 ps
module para_mach_d(
clk,
wada,wadb,wadc,wadd,wade,wadf,wadg,wadh,
wreqa,wreqb,wreqc,wreqd,wreqe,wreqf,wreqg,wreqh,
wnuma,wnumb,wnumc,wnumd,wnume,wnumf,wnumg,wnumh,
wack,
rada,radb,radc,radd,rade,radf,radg,radh,
rreqa,rreqb,rreqc,rreqd,rreqe,rreqf,rreqg,rreqh,
rnuma,rnumb,rnumc,rnumd,rnume,rnumf,rnumg,rnumh,
rack,
w0sel,w1sel,w2sel,
ch_num,ch_rw,ch_addr,ch_ack,ch_req,ch_sur,
mach,
req_mach,
SelSur
);
input clk;
input [20:0] wada,wadb,wadc,wadd,wade,wadf,wadg,wadh;
input wreqa,wreqb,wreqc,wreqd,wreqe,wreqf,wreqg,wreqh;
input [7:0] wnuma,wnumb,wnumc,wnumd,wnume,wnumf,wnumg,wnumh;
output [7:0] wack;
input [20:0] rada,radb,radc,radd,rade,radf,radg,radh;
input rreqa,rreqb,rreqc,rreqd,rreqe,rreqf,rreqg,rreqh;
input [7:0] rnuma,rnumb,rnumc,rnumd,rnume,rnumf,rnumg,rnumh;
output [7:0] rack;
output [7:0] ch_num;
output [20:0] ch_addr;
output ch_rw;
output ch_req;
input ch_ack;
output [3:0] w0sel;
output [1:0] w1sel;
output w2sel;
output [2:0] ch_sur;
output [7:0] mach;
output[3:0] req_mach;
output [2:0] SelSur;
parameter [7:0] LockStatus =8'h01,
PipeDelay =8'h02,
JudgeInt =8'h04,
WaitReqIdle =8'h08,
WaitReqSend =8'h10;
reg [7:0] mach;
parameter[3:0] wait_req_ok =4'h01,
set_req =4'h02,
wait_req_ack=4'h04;
reg[3:0] req_mach;
/*
reg [20:0] syn_rada,syn_radb,syn_radc,syn_radd,syn_rade,syn_radf,syn_radg,syn_radh;
reg [7:0] syn_rnuma,syn_rnumb,syn_rnumc,syn_rnumd,syn_rnume,syn_rnumf,syn_rnumg,syn_rnumh;
reg [20:0] syn_wada,syn_wadb,syn_wadc,syn_wadd,syn_wade,syn_wadf,syn_wadg,syn_wadh;
reg [7:0] syn_wnuma,syn_wnumb,syn_wnumc,syn_wnumd,syn_wnume,syn_wnumf,syn_wnumg,syn_wnumh;
*/
reg[7:0] Delay;
always @(posedge clk)
if(mach==PipeDelay)
Delay<= #1 Delay+8'd1;
else
Delay<= #1 8'd0;
wire LockReq;
assign LockReq=(mach==LockStatus);
//assign LockReq=(Delay==8'h04);
reg cur_ch_req;
reg [7:0] w_req_syn,r_req_syn;
//----------------------------鎖存中斷信號(hào)------------------------------------------------------
always @(posedge clk)begin
if(LockReq)begin
cur_ch_req <= #1 ch_req;
w_req_syn<= #1 {wreqh,wreqg,wreqf,wreqe,wreqd,wreqc,wreqb,wreqa };
r_req_syn<= #1 {rreqh,rreqg,rreqf,rreqe,rreqd,rreqc,rreqb,rreqa };
end
else begin
cur_ch_req <= #1 cur_ch_req;
w_req_syn<= #1 w_req_syn;
r_req_syn<= #1 r_req_syn;
end
end
wire [7:0] w_req_en,r_req_en;
assign w_req_en[0] =w_req_syn[0] & (cur_ch_req ? ~((ch_sur==3'd0)& (ch_rw==1'b0)) : 1'b1);
assign w_req_en[1] =w_req_syn[1] & (cur_ch_req ? ~((ch_sur==3'd1)& (ch_rw==1'b0)) : 1'b1);
assign w_req_en[2] =w_req_syn[2] & (cur_ch_req ? ~((ch_sur==3'd2)& (ch_rw==1'b0)) : 1'b1);
assign w_req_en[3] =w_req_syn[3] & (cur_ch_req ? ~((ch_sur==3'd3)& (ch_rw==1'b0)) : 1'b1);
assign w_req_en[4] =w_req_syn[4] & (cur_ch_req ? ~((ch_sur==3'd4)& (ch_rw==1'b0)) : 1'b1);
assign w_req_en[5] =w_req_syn[5] & (cur_ch_req ? ~((ch_sur==3'd5)& (ch_rw==1'b0)) : 1'b1);
assign w_req_en[6] =w_req_syn[6] & (cur_ch_req ? ~((ch_sur==3'd6)& (ch_rw==1'b0)) : 1'b1);
assign w_req_en[7] =w_req_syn[7] & (cur_ch_req ? ~((ch_sur==3'd7)& (ch_rw==1'b0)) : 1'b1);
assign r_req_en[0] =r_req_syn[0] & (cur_ch_req ? ~((ch_sur==3'd0)& (ch_rw==1'b1)) : 1'b1);
assign r_req_en[1] =r_req_syn[1] & (cur_ch_req ? ~((ch_sur==3'd1)& (ch_rw==1'b1)) : 1'b1);
assign r_req_en[2] =r_req_syn[2] & (cur_ch_req ? ~((ch_sur==3'd2)& (ch_rw==1'b1)) : 1'b1);
assign r_req_en[3] =r_req_syn[3] & (cur_ch_req ? ~((ch_sur==3'd3)& (ch_rw==1'b1)) : 1'b1);
assign r_req_en[4] =r_req_syn[4] & (cur_ch_req ? ~((ch_sur==3'd4)& (ch_rw==1'b1)) : 1'b1);
assign r_req_en[5] =r_req_syn[5] & (cur_ch_req ? ~((ch_sur==3'd5)& (ch_rw==1'b1)) : 1'b1);
assign r_req_en[6] =r_req_syn[6] & (cur_ch_req ? ~((ch_sur==3'd6)& (ch_rw==1'b1)) : 1'b1);
assign r_req_en[7] =r_req_syn[7] & (cur_ch_req ? ~((ch_sur==3'd7)& (ch_rw==1'b1)) : 1'b1);
//-----------------------讀寫信號(hào)---------------------------------------------
//-----------------------通道信號(hào)---------------------------------------------
//-----------------------地址信號(hào)---------------------------------------------
//-----------------------寫流水信號(hào)0------------------------------------------
//-----------------------寫流水信號(hào)1------------------------------------------
//-----------------------寫流水信號(hào)2------------------------------------------
//-----------------------寫數(shù)目-----------------------------------------------
wire SelRw;
wire[2:0] SelSur;
wire[20:0] SelAddr;
wire[3:0] SelW0Sel;
wire[1:0] SelW1Sel;
wire SelW2Sel;
assign SelRw= r_req_en[0] ? 1'b1 : //gui0 read
( r_req_en[1] ? 1'b1 : //gui1 read
( w_req_en[0] ? 1'b0 : //pixel trans
( r_req_en[2] ? 1'b1 : //nios read
( w_req_en[1] ? 1'b0 : //nios write
( w_req_en[2] ? 1'b0 :
( r_req_en[3] ? 1'b1 :
( w_req_en[3] ? 1'b0 :
( w_req_en[4] ? 1'b0 :
( r_req_en[4] ? 1'b1 :
( r_req_en[5] ? 1'b1 :
( r_req_en[6] ? 1'b1 :
( r_req_en[7] ? 1'b1 :
( w_req_en[5] ? 1'b0 :
( w_req_en[6] ? 1'b0 :
( w_req_en[7] ? 1'b0 : 1'b1))))) )))))))) ));
assign SelSur= r_req_en[0] ? 3'd0 :
( r_req_en[1] ? 3'd1 :
( w_req_en[0] ? 3'd0 :
( r_req_en[2] ? 3'd2 :
( w_req_en[1] ? 3'd1 :
( w_req_en[2] ? 3'd2 :
( r_req_en[3] ? 3'd3 :
( w_req_en[3] ? 3'd3 :
( w_req_en[4] ? 3'd4 :
( r_req_en[4] ? 3'd4 :
( r_req_en[5] ? 3'd5 :
( r_req_en[6] ? 3'd6 :
( r_req_en[7] ? 3'd7 :
( w_req_en[5] ? 3'd5 :
( w_req_en[6] ? 3'd6 :
( w_req_en[7] ? 3'd7 : 3'd0))))) )))))))) ));
assign SelAddr=SelRw ?
(
((SelSur==3'd0) ? rada : 21'd0)
|((SelSur==3'd1) ? radb : 21'd0)
|((SelSur==3'd2) ? radc : 21'd0)
|((SelSur==3'd3) ? radd : 21'd0)
|((SelSur==3'd4) ? rade : 21'd0)
|((SelSur==3'd5) ? radf : 21'd0)
|((SelSur==3'd6) ? radg : 21'd0)
|((SelSur==3'd7) ? radh : 21'd0)
)
:
(
((SelSur==3'd0) ? wada : 21'd0)
|((SelSur==3'd1) ? wadb : 21'd0)
|((SelSur==3'd2) ? wadc : 21'd0)
|((SelSur==3'd3) ? wadd : 21'd0)
|((SelSur==3'd4) ? wade : 21'd0)
|((SelSur==3'd5) ? wadf : 21'd0)
|((SelSur==3'd6) ? wadg : 21'd0)
|((SelSur==3'd7) ? wadh : 21'd0)
);
assign SelW0Sel=
((SelSur==3'd0) ? 4'b0001 : 4'd0)
|((SelSur==3'd1) ? 4'b0000 : 4'd0)
|((SelSur==3'd2) ? 4'b0010 : 4'd0)
|((SelSur==3'd3) ? 4'b0000 : 4'd0)
|((SelSur==3'd4) ? 4'b0100 : 4'd0)
|((SelSur==3'd5) ? 4'b0000 : 4'd0)
|((SelSur==3'd6) ? 4'b1000 : 4'd0)
|((SelSur==3'd7) ? 4'b0000 : 4'd0);
assign SelW1Sel=
((SelSur==3'd0) ? 2'b01 : 2'b0)
|((SelSur==3'd1) ? 2'b01 : 2'b0)
|((SelSur==3'd2) ? 2'b00 : 2'b0)
|((SelSur==3'd3) ? 2'b00 : 2'b0)
|((SelSur==3'd4) ? 2'b10 : 2'b0)
|((SelSur==3'd5) ? 2'b10 : 2'b0)
|((SelSur==3'd6) ? 2'b00 : 2'b0)
|((SelSur==3'd7) ? 2'b00 : 2'b0);
assign SelW2Sel=
((SelSur==3'd0) ? 1'b1 : 1'b0)
|((SelSur==3'd1) ? 1'b1 : 1'b0)
|((SelSur==3'd2) ? 1'b1 : 1'b0)
|((SelSur==3'd3) ? 1'b1 : 1'b0)
|((SelSur==3'd4) ? 1'b0 : 1'b0)
|((SelSur==3'd5) ? 1'b0 : 1'b0)
|((SelSur==3'd6) ? 1'b0 : 1'b0)
|((SelSur==3'd7) ? 1'b0 : 1'b0);
wire[7:0] SelNum;
assign SelNum= SelRw ?
(
((SelSur==3'd0) ? rnuma : 8'd0)
|((SelSur==3'd1) ? rnumb : 8'd0)
|((SelSur==3'd2) ? rnumc : 8'd0)
|((SelSur==3'd3) ? rnumd : 8'd0)
|((SelSur==3'd4) ? rnume : 8'd0)
|((SelSur==3'd5) ? rnumf : 8'd0)
|((SelSur==3'd6) ? rnumg : 8'd0)
|((SelSur==3'd7) ? rnumh : 8'd0)
)
:
(
((SelSur==3'd0) ? wnuma : 8'd0)
|((SelSur==3'd1) ? wnumb : 8'd0)
|((SelSur==3'd2) ? wnumc : 8'd0)
|((SelSur==3'd3) ? wnumd : 8'd0)
|((SelSur==3'd4) ? wnume : 8'd0)
|((SelSur==3'd5) ? wnumf : 8'd0)
|((SelSur==3'd6) ? wnumg : 8'd0)
|((SelSur==3'd7) ? wnumh : 8'd0)
);
//---------------------寫應(yīng)答--------------------------------------------------
//---------------------讀應(yīng)答-----------------------------------------------
reg [7:0] wack,rack;
always @(posedge clk)begin
wack[0]<= #1 (ch_sur==3'd0) & ch_ack & ~ch_rw;
wack[1]<= #1 (ch_sur==3'd1) & ch_ack & ~ch_rw;
wack[2]<= #1 (ch_sur==3'd2) & ch_ack & ~ch_rw;
wack[3]<= #1 (ch_sur==3'd3) & ch_ack & ~ch_rw;
wack[4]<= #1 (ch_sur==3'd4) & ch_ack & ~ch_rw;
wack[5]<= #1 (ch_sur==3'd5) & ch_ack & ~ch_rw;
wack[6]<= #1 (ch_sur==3'd6) & ch_ack & ~ch_rw;
wack[7]<= #1 (ch_sur==3'd7) & ch_ack & ~ch_rw;
end
rack[0]<= #1 (ch_sur==3'd0) & ch_ack & ch_rw;
rack[1]<= #1 (ch_sur==3'd1) & ch_ack & ch_rw;
rack[2]<= #1 (ch_sur==3'd2) & ch_ack & ch_rw;
rack[3]<= #1 (ch_sur==3'd3) & ch_ack & ch_rw;
rack[4]<= #1 (ch_sur==3'd4) & ch_ack & ch_rw;
rack[5]<= #1 (ch_sur==3'd5) & ch_ack & ch_rw;
rack[6]<= #1 (ch_sur==3'd6) & ch_ack & ch_rw;
rack[7]<= #1 (ch_sur==3'd7) & ch_ack & ch_rw;
end
wire req_exist;
assign req_exist=((w_req_en | r_req_en)!=8'd0);
always @(posedge clk)
casex(mach)
LockStatus:begin
mach<= #1 PipeDelay;
end
PipeDelay:begin
if(Delay>=8'h10)
mach<= #1 JudgeInt;
else
mach<= #1 PipeDelay;
end
JudgeInt:begin
if(req_exist)begin
mach<= #1 WaitReqIdle;
end
else
mach<= #1 LockStatus;
end
WaitReqIdle:begin
if(ch_req || ch_ack)begin
mach<= #1 WaitReqIdle;
end
else begin
mach<= #1 WaitReqSend;
end
end
WaitReqSend:begin
if(ch_req)
mach<= #1 LockStatus;
else
mach<= #1 WaitReqSend;
end
default:
mach<= #1 LockStatus;
endcase
wire req_ok;
assign req_ok=(mach==WaitReqSend);
reg ReqEn;
reg LockData;
always @(posedge clk)
case(req_mach)
wait_req_ok:begin
ReqEn<= #1 1'b0;
if(req_ok)begin
LockData<= #1 1'b1;
req_mach<= #1 set_req;
end
else begin
LockData<= #1 1'b0;
req_mach<= #1 wait_req_ok;
end
end
set_req:begin
LockData<= #1 1'b0;
if(ch_req)begin
ReqEn<= #1 1'b0;
req_mach<= #1 wait_req_ack;
end
else begin
ReqEn<= #1 1'b1;
req_mach<= #1 set_req;
end
end
wait_req_ack:begin
ReqEn<= #1 1'b0;
if(ch_req || ch_ack)
req_mach<= #1 wait_req_ack;
else
req_mach<= #1 wait_req_ok;
end
default:
req_mach<= #1 wait_req_ok;
endcase
reg ch_req;
always @(posedge clk or posedge ch_ack)
if(ch_ack)
ch_req<= #1 1'b0;
else
if(ReqEn)
ch_req<= #1 1'b1;
else
ch_req<= #1 ch_req;
reg ch_rw;
reg[20:0] ch_addr;
reg[7:0] ch_num;
reg[2:0] ch_sur;
reg [3:0] w0sel;
reg [1:0] w1sel;
reg w2sel;
always @(posedge clk)
if(LockData)begin
ch_sur <= #1 SelSur;
ch_rw <= #1 SelRw;
ch_addr <= #1 SelAddr;
ch_num <= #1 SelNum;
w0sel <= #1 SelW0Sel;
w1sel <= #1 SelW1Sel;
w2sel <= #1 SelW2Sel;
end
else begin
ch_sur <= #1 ch_sur;
ch_rw <= #1 ch_rw;
ch_addr <= #1 ch_addr;
ch_num <= #1 ch_num;
w0sel <= #1 w0sel;
w1sel <= #1 w1sel;
w2sel <= #1 w2sel;
end
endmodule
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