?? rw_sd_mach.pin
字號:
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
----------------------------------------------------------------------------
CHIP "rw_sd_mach" ASSIGNED TO AN EPF10K10TC144-3
TCK : 1
CONF_DONE : 2
nCEO : 3
TDO : 4
VCCIO : 5
VCCINT : 6
add14 : 7
add3 : 8
data_req : 9
add15 : 10
ch_addr10 : 11
add12 : 12
ch_addr9 : 13
add16 : 14
GNDIO : 15
GNDINT : 16
add0 : 17
add21 : 18
ch_addr14 : 19
add24 : 20
ch_addr18 : 21
ch_addr17 : 22
add22 : 23
VCCIO : 24
VCCINT : 25
ch_num2 : 26
ch_num4 : 27
ch_addr6 : 28
ch_addr2 : 29
ch_num3 : 30
ch_num7 : 31
ch_num6 : 32
ch_addr4 : 33
TMS : 34
nSTATUS : 35
RESERVED : 36
RESERVED : 37
RESERVED : 38
RESERVED : 39
GNDIO : 40
ch_addr13 : 41
RESERVED : 42
RESERVED : 43
RESERVED : 44
VCCIO : 45
add23 : 46
ch_addr12 : 47
RESERVED : 48
ch_addr8 : 49
GNDIO : 50
RESERVED : 51
VCCINT : 52
VCCINT : 53
data_cycle : 54
clk : 55
ch_rw : 56
GNDINT : 57
GNDINT : 58
dp_addr0 : 59
RESERVED : 60
VCCIO : 61
RESERVED : 62
dp_addr3 : 63
add8 : 64
RESERVED : 65
GNDIO : 66
ch_addr7 : 67
rs_ready : 68
RESERVED : 69
add9 : 70
VCCIO : 71
RESERVED : 72
dp_rden : 73
nCONFIG : 74
VCCINT : 75
MSEL1 : 76
MSEL0 : 77
add6 : 78
add11 : 79
add4 : 80
ch_ack : 81
ch_num1 : 82
add5 : 83
GNDINT : 84
GNDIO : 85
add18 : 86
add2 : 87
add1 : 88
ch_addr20 : 89
add19 : 90
ch_addr16 : 91
add20 : 92
VCCINT : 93
VCCIO : 94
dp_addr7 : 95
ch_addr11 : 96
dp_addr5 : 97
dp_addr4 : 98
dp_addr2 : 99
dp_wren : 100
dp_addr6 : 101
wr_l : 102
GNDINT : 103
GNDIO : 104
TDI : 105
nCE : 106
DCLK : 107
DATA0 : 108
ch_num0 : 109
RESERVED : 110
ch_addr15 : 111
ch_num5 : 112
RESERVED : 113
ch_addr3 : 114
VCCIO : 115
RESERVED : 116
add10 : 117
RESERVED : 118
RESERVED : 119
ch_addr5 : 120
add7 : 121
dp_addr1 : 122
VCCINT : 123
state_cntr0 : 124
ch_addr1 : 125
ch_addr0 : 126
GNDINT : 127
RESERVED : 128
GNDIO : 129
RESERVED : 130
RESERVED : 131
RESERVED : 132
RESERVED : 133
VCCIO : 134
add13 : 135
add17 : 136
ch_addr19 : 137
RESERVED : 138
GNDIO : 139
ch_req : 140
RESERVED : 141
RESERVED : 142
sdram_setup : 143
RESERVED : 144
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