{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 24 21:18:43 2008 " "Info: Processing started: Thu Jan 24 21:18:43 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mem_ctrl1 -c mem_ctrl1 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mem_ctrl1 -c mem_ctrl1 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "mem_ctrl1.v 1 1 " "Warning: Using design file mem_ctrl1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 mem_ctrl1 " "Info: Found entity 1: mem_ctrl1" {  } { { "mem_ctrl1.v" "" { Text "D:/newsdram/mem_ctrl1.v" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "mem_ctrl1 " "Info: Elaborating entity \"mem_ctrl1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "r_ch_sur mem_ctrl1.v(132) " "Warning (10036): Verilog HDL or VHDL warning at mem_ctrl1.v(132): object \"r_ch_sur\" assigned a value but never read" {  } { { "mem_ctrl1.v" "" { Text "D:/newsdram/mem_ctrl1.v" 132 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "wr_sel_pipe.v 1 1 " "Warning: Using design file wr_sel_pipe.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 wr_sel_pipe " "Info: Found entity 1: wr_sel_pipe" {  } { { "wr_sel_pipe.v" "" { Text "D:/newsdram/wr_sel_pipe.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "wr_sel_pipe wr_sel_pipe:wr_sel_pile1 " "Info: Elaborating entity \"wr_sel_pipe\" for hierarchy \"wr_sel_pipe:wr_sel_pile1\"" {  } { { "mem_ctrl1.v" "wr_sel_pile1" { Text "D:/newsdram/mem_ctrl1.v" 81 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "para_mach_d.v 1 1 " "Warning: Using design file para_mach_d.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 para_mach_d " "Info: Found entity 1: para_mach_d" {  } { { "para_mach_d.v" "" { Text "D:/newsdram/para_mach_d.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "para_mach_d para_mach_d:para_mach_inst " "Info: Elaborating entity \"para_mach_d\" for hierarchy \"para_mach_d:para_mach_inst\"" {  } { { "mem_ctrl1.v" "para_mach_inst" { Text "D:/newsdram/mem_ctrl1.v" 130 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "para_mach_d.v(268) " "Info (10264): Verilog HDL Case Statement information at para_mach_d.v(268): all case item expressions in this case statement are onehot" {  } { { "para_mach_d.v" "" { Text "D:/newsdram/para_mach_d.v" 268 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "para_mach_d.v(307) " "Info (10264): Verilog HDL Case Statement information at para_mach_d.v(307): all case item expressions in this case statement are onehot" {  } { { "para_mach_d.v" "" { Text "D:/newsdram/para_mach_d.v" 307 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sd_if.v 1 1 " "Warning: Using design file sd_if.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sd_if " "Info: Found entity 1: sd_if" {  } { { "sd_if.v" "" { Text "D:/newsdram/sd_if.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sd_if sd_if:sd_if1 " "Info: Elaborating entity \"sd_if\" for hierarchy \"sd_if:sd_if1\"" {  } { { "mem_ctrl1.v" "sd_if1" { Text "D:/newsdram/mem_ctrl1.v" 169 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "term_l sd_if.v(46) " "Warning (10036): Verilog HDL or VHDL warning at sd_if.v(46): object \"term_l\" assigned a value but never read" {  } { { "sd_if.v" "" { Text "D:/newsdram/sd_if.v" 46 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "rw_sd_mach.v 1 1 " "Warning: Using design file rw_sd_mach.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 rw_sd_mach " "Info: Found entity 1: rw_sd_mach" {  } { { "rw_sd_mach.v" "" { Text "D:/newsdram/rw_sd_mach.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_sd_mach sd_if:sd_if1\|rw_sd_mach:u1 " "Info: Elaborating entity \"rw_sd_mach\" for hierarchy \"sd_if:sd_if1\|rw_sd_mach:u1\"" {  } { { "sd_if.v" "u1" { Text "D:/newsdram/sd_if.v" 59 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sd_top.v 1 1 " "Warning: Using design file sd_top.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sd_top " "Info: Found entity 1: sd_top" {  } { { "sd_top.v" "" { Text "D:/newsdram/sd_top.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sd_top sd_if:sd_if1\|sd_top:sd_top1 " "Info: Elaborating entity \"sd_top\" for hierarchy \"sd_if:sd_if1\|sd_top:sd_top1\"" {  } { { "sd_if.v" "sd_top1" { Text "D:/newsdram/sd_if.v" 79 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sd_cnfg.v 1 1 " "Warning: Using design file sd_cnfg.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sd_cnfg " "Info: Found entity 1: sd_cnfg" {  } { { "sd_cnfg.v" "" { Text "D:/newsdram/sd_cnfg.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sd_cnfg sd_if:sd_if1\|sd_top:sd_top1\|sd_cnfg:u1 " "Info: Elaborating entity \"sd_cnfg\" for hierarchy \"sd_if:sd_if1\|sd_top:sd_top1\|sd_cnfg:u1\"" {  } { { "sd_top.v" "u1" { Text "D:/newsdram/sd_top.v" 85 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "nop1 sd_cnfg.v(42) " "Warning (10036): Verilog HDL or VHDL warning at sd_cnfg.v(42): object \"nop1\" assigned a value but never read" {  } { { "sd_cnfg.v" "" { Text "D:/newsdram/sd_cnfg.v" 42 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "nop3 sd_cnfg.v(46) " "Warning (10036): Verilog HDL or VHDL warning at sd_cnfg.v(46): object \"nop3\" assigned a value but never read" {  } { { "sd_cnfg.v" "" { Text "D:/newsdram/sd_cnfg.v" 46 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sd_state.v 1 1 " "Warning: Using design file sd_state.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sd_state " "Info: Found entity 1: sd_state" {  } { { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sd_state sd_if:sd_if1\|sd_top:sd_top1\|sd_state:u2 " "Info: Elaborating entity \"sd_state\" for hierarchy \"sd_if:sd_if1\|sd_top:sd_top1\|sd_state:u2\"" {  } { { "sd_top.v" "u2" { Text "D:/newsdram/sd_top.v" 102 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "cas_time sd_state.v(55) " "Warning (10036): Verilog HDL or VHDL warning at sd_state.v(55): object \"cas_time\" assigned a value but never read" {  } { { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 55 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}