{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "sd_state.v(65) " "Info (10264): Verilog HDL Case Statement information at sd_state.v(65): all case item expressions in this case statement are onehot" {  } { { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 65 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sd_rfrsh.v 1 1 " "Warning: Using design file sd_rfrsh.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sd_rfrsh " "Info: Found entity 1: sd_rfrsh" {  } { { "sd_rfrsh.v" "" { Text "D:/newsdram/sd_rfrsh.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sd_rfrsh sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3 " "Info: Elaborating entity \"sd_rfrsh\" for hierarchy \"sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\"" {  } { { "sd_top.v" "u3" { Text "D:/newsdram/sd_top.v" 109 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "cnt_110 sd_rfrsh.v(21) " "Warning (10036): Verilog HDL or VHDL warning at sd_rfrsh.v(21): object \"cnt_110\" assigned a value but never read" {  } { { "sd_rfrsh.v" "" { Text "D:/newsdram/sd_rfrsh.v" 21 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "cnt_80 sd_rfrsh.v(22) " "Warning (10036): Verilog HDL or VHDL warning at sd_rfrsh.v(22): object \"cnt_80\" assigned a value but never read" {  } { { "sd_rfrsh.v" "" { Text "D:/newsdram/sd_rfrsh.v" 22 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "cnt_50 sd_rfrsh.v(24) " "Warning (10036): Verilog HDL or VHDL warning at sd_rfrsh.v(24): object \"cnt_50\" assigned a value but never read" {  } { { "sd_rfrsh.v" "" { Text "D:/newsdram/sd_rfrsh.v" 24 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "cnt_40 sd_rfrsh.v(25) " "Warning (10036): Verilog HDL or VHDL warning at sd_rfrsh.v(25): object \"cnt_40\" assigned a value but never read" {  } { { "sd_rfrsh.v" "" { Text "D:/newsdram/sd_rfrsh.v" 25 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "cnt_33 sd_rfrsh.v(26) " "Warning (10036): Verilog HDL or VHDL warning at sd_rfrsh.v(26): object \"cnt_33\" assigned a value but never read" {  } { { "sd_rfrsh.v" "" { Text "D:/newsdram/sd_rfrsh.v" 26 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "count sd_rfrsh.v(27) " "Warning (10036): Verilog HDL or VHDL warning at sd_rfrsh.v(27): object \"count\" assigned a value but never read" {  } { { "sd_rfrsh.v" "" { Text "D:/newsdram/sd_rfrsh.v" 27 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sd_sig.v 1 1 " "Warning: Using design file sd_sig.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 sd_sig " "Info: Found entity 1: sd_sig" {  } { { "sd_sig.v" "" { Text "D:/newsdram/sd_sig.v" 22 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sd_sig sd_if:sd_if1\|sd_top:sd_top1\|sd_sig:u4 " "Info: Elaborating entity \"sd_sig\" for hierarchy \"sd_if:sd_if1\|sd_top:sd_top1\|sd_sig:u4\"" {  } { { "sd_top.v" "u4" { Text "D:/newsdram/sd_top.v" 137 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "sd_add sd_top1 11 12 " "Warning: Port \"sd_add\" on the entity instantiation of \"sd_top1\" is connected to a signal of width 11. The formal width of the signal in the module is 12.  Extra bits will be left dangling without any fanout logic." {  } { { "sd_if.v" "sd_top1" { Text "D:/newsdram/sd_if.v" 79 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "para_mach_d:para_mach_inst\|mach\[7\] data_in GND " "Warning: Reduced register \"para_mach_d:para_mach_inst\|mach\[7\]\" with stuck data_in port to stuck value GND" {  } { { "para_mach_d.v" "" { Text "D:/newsdram/para_mach_d.v" 268 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "para_mach_d:para_mach_inst\|mach\[6\] data_in GND " "Warning: Reduced register \"para_mach_d:para_mach_inst\|mach\[6\]\" with stuck data_in port to stuck value GND" {  } { { "para_mach_d.v" "" { Text "D:/newsdram/para_mach_d.v" 268 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "para_mach_d:para_mach_inst\|mach\[5\] data_in GND " "Warning: Reduced register \"para_mach_d:para_mach_inst\|mach\[5\]\" with stuck data_in port to stuck value GND" {  } { { "para_mach_d.v" "" { Text "D:/newsdram/para_mach_d.v" 268 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "para_mach_d:para_mach_inst\|req_mach\[3\] data_in GND " "Warning: Reduced register \"para_mach_d:para_mach_inst\|req_mach\[3\]\" with stuck data_in port to stuck value GND" {  } { { "para_mach_d.v" "" { Text "D:/newsdram/para_mach_d.v" 307 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0\"" {  } { { "sd_rfrsh.v" "" { Text "D:/newsdram/sd_rfrsh.v" 36 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0\|addcore:adder sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 266 4 0 } } { "sd_rfrsh.v" "" { Text "D:/newsdram/sd_rfrsh.v" 36 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 11 " "Info: Parameter \"LPM_WIDTH\" = \"11\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "sd_rfrsh.v" "" { Text "D:/newsdram/sd_rfrsh.v" 36 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "sd_rfrsh.v" "" { Text "D:/newsdram/sd_rfrsh.v" 36 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 11 " "Info: Parameter \"LPM_WIDTH\" = \"11\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "sd_rfrsh.v" "" { Text "D:/newsdram/sd_rfrsh.v" 36 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 120 6 0 } } { "sd_rfrsh.v" "" { Text "D:/newsdram/sd_rfrsh.v" 36 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"sd_if:sd_if1\|sd_top:sd_top1\|sd_rfrsh:u3\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 11 " "Info: Parameter \"LPM_WIDTH\" = \"11\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "sd_rfrsh.v" "" { Text "D:/newsdram/sd_rfrsh.v" 36 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}