`timescale 1 ns /  100 ps
module sd_state(
                clk,
                rst_l,

                fresh_req,
                load_req,
				charge_req,
				data_req,	
					
				idle_cycle,		
				load_cycle,	
				data_cycle, 		
				fresh_cycle, 		
				charge_cycle,
				
				state_cntr
			);
//--------------------------------------------------------------------
// inputs
input           clk;
input           rst_l;

input           fresh_req;
input           load_req;
input           charge_req;
input			data_req;

output			idle_cycle;
output			load_cycle;	
output			data_cycle;		
output			fresh_cycle;	
output			charge_cycle;

input[7:0]		state_cntr;

//--------------------------------------------------------------------
reg    [4:0]    sdram_cycle;

assign   {	
			charge_cycle,
			fresh_cycle,
			data_cycle,	
			load_cycle,
			idle_cycle			
				}=sdram_cycle[4:0];	
//--------------------------------------------------------------------
// state parameters
parameter 	idle 		= 5'b00001;
parameter	load		= 5'b00010;
parameter 	data 		= 5'b00100;
parameter 	fresh 		= 5'b01000;
parameter 	charge		= 5'b10000;

//--------------------------------------------------------------------
// state machine
reg		charge_on;
always @(posedge clk or negedge rst_l)
   	if (!rst_l)begin
      	sdram_cycle <= #1    idle;
		charge_on<= #1  1'b0;
   	end
   	else 
		case (sdram_cycle)
      	idle :
		            if (charge_req || charge_on)
                     	sdram_cycle <= #1    charge;
					else if (fresh_req)
              			sdram_cycle <= #1    fresh;
                  	else if (load_req)
                     	sdram_cycle <= #1    load;
                  	else if(data_req)
                     	sdram_cycle <= #1    data;                     
      	load : 
					if (state_cntr[3])
                     	sdram_cycle <= #1    idle;
      	data : 
					if (!data_req)begin
						charge_on<= #1  1'b1;
                     	sdram_cycle <= #1    idle;	
					end
					else
						charge_on<= #1  1'b0;
      	charge:		begin
					charge_on<= #1  1'b0;
					if(state_cntr[3])
						sdram_cycle <= #1    idle;
		end
      	fresh : 
					if (state_cntr[3])
                     	sdram_cycle <= #1    idle;
      	default:    
					sdram_cycle <= #1    idle;
      	endcase
//-------------------------------------------------------------------
endmodule