module sd_if(
				ch_req,ch_addr,ch_rw,ch_num,ch_ack,ch_dqm,
				dp_addr,dp_wren,dp_rden,
				clk,                // sdram clock
				rst_l,              // reset signal
				sdram_en,
				sd_cke,             // sdram clock enable
				sd_ba,              // sdram bank address
				sd_cs0_l,           // sdram chip select 0
				sd_ras_l,           // sdram row address
				sd_cas_l,           // sdram column select
				sd_we_l,            // sdram write enable
				sd_add,             // sdram address
				sd_dqm,             // sdram data qual mask
                sdram_setup,		// sdram setup completed
				rs_ready
	);
input			sdram_en;
input          	clk;
input          	rst_l;
input			ch_req;
input	[20:0]	ch_addr;
input			ch_rw;
input	[7:0]	ch_num;
output			ch_ack;
input	[15:0]	ch_dqm;
output	[7:0]	dp_addr;

output			dp_wren,dp_rden;

output         	sd_cke;
output [1:0]   	sd_ba;
output         	sd_cs0_l,
               	sd_ras_l,
				sd_cas_l,
				sd_we_l;
output [10:0]  	sd_add;
output [15:0]   sd_dqm;              // change width for data width
output          sdram_setup;
output			rs_ready;

wire			wr_l;
wire			sdram_en;
wire  [15:0]   	byte_en;

wire			rs_ready;
wire			data_cycle;
wire[24:0]	add;
wire[7:0]	state_cntr;

wire	data_req;
rw_sd_mach u1(
		.rst_l(rst_l),.clk(clk),
		.ch_req(ch_req),.ch_addr(ch_addr),.ch_rw(ch_rw),.ch_num(ch_num),.ch_ack(ch_ack),
		.dp_addr(dp_addr),.dp_wren(dp_wren),.dp_rden(dp_rden),
		.data_req(data_req),
		.add(add),.wr_l(wr_l),.data_cycle(data_cycle),
		.rs_ready(rs_ready),.sdram_setup(sdram_setup),
		.state_cntr(state_cntr)
	);
wire[11:0]	tsd_add;
assign	sd_add=tsd_add[10:0];
sd_top		sd_top1( 		
				.data_req(data_req),         // sdram select
				.wr_l(wr_l),               	// write strobe
				.sdram_en(sdram_en),		// sdram enable
				.clk(clk),
				.rst_l(rst_l),              // reset signal
				.byte_en(ch_dqm),          // byte enables
				.add(add),                	// address bus
				.sd_cke(sd_cke),            // sdram clock enable
				.sd_ba(sd_ba),              // sdram bank address
				.sd_cs0_l(sd_cs0_l),        // sdram chip select 0
				.sd_ras_l(sd_ras_l),        // sdram row address
				.sd_cas_l(sd_cas_l),        // sdram column select
				.sd_we_l(sd_we_l),          // sdram write enable
				.sd_add(tsd_add),            // sdram address
				.sd_dqm(sd_dqm),            // sdram data qual mask
                .sdram_setup(sdram_setup),	// sdram setup completed
				.rs_ready(rs_ready),
				.data_cycle(data_cycle)
				); 
  
endmodule