-- Equation name is '_LC7_B3', type is buried 
!_LC7_B3 = _LC7_B3~NOT;
_LC7_B3~NOT = DFFE( _EQ046, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ046 =  load_cycle
         #  charge_cycle
         #  fresh_cycle
         #  data_cycle;

-- Node name is ':511' 
-- Equation name is '_LC3_B3', type is buried 
!_LC3_B3 = _LC3_B3~NOT;
_LC3_B3~NOT = DFFE( _EQ047, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ047 =  fresh_cycle &  _LC7_B7
         # !_LC4_B3 &  _LC7_B7
         #  data_cycle &  _LC7_B7;

-- Node name is ':532' 
-- Equation name is '_LC1_A3', type is buried 
_LC1_A3  = LCELL( _EQ048);
  _EQ048 = !_LC7_A3 &  op_active;

-- Node name is ':550' 
-- Equation name is '_LC7_A1', type is buried 
_LC7_A1  = LCELL( _EQ049);
  _EQ049 = !op_num6 &  op_num7
         # !_LC4_A1 &  op_num7
         #  _LC1_A3 &  _LC4_A1 &  op_num6 & !op_num7
         # !_LC1_A3 &  op_num7;

-- Node name is ':551' 
-- Equation name is '_LC5_A1', type is buried 
_LC5_A1  = LCELL( _EQ050);
  _EQ050 = !_LC4_A1 &  op_num6
         #  _LC1_A3 &  _LC4_A1 & !op_num6
         # !_LC1_A3 &  op_num6;

-- Node name is ':552' 
-- Equation name is '_LC2_A8', type is buried 
_LC2_A8  = LCELL( _EQ051);
  _EQ051 = !_LC8_A1 &  op_num5
         #  _LC1_A3 &  _LC8_A1 & !op_num5
         # !_LC1_A3 &  op_num5;

-- Node name is ':553' 
-- Equation name is '_LC3_A1', type is buried 
_LC3_A1  = LCELL( _EQ052);
  _EQ052 = !op_num3 &  op_num4
         # !_LC1_A6 &  op_num4
         #  _LC1_A3 &  _LC1_A6 &  op_num3 & !op_num4
         # !_LC1_A3 &  op_num4;

-- Node name is ':554' 
-- Equation name is '_LC3_A3', type is buried 
_LC3_A3  = LCELL( _EQ053);
  _EQ053 = !_LC1_A6 &  op_num3
         #  _LC1_A3 &  _LC1_A6 & !op_num3
         # !_LC1_A3 &  op_num3;

-- Node name is ':555' 
-- Equation name is '_LC6_A6', type is buried 
_LC6_A6  = LCELL( _EQ054);
  _EQ054 = !op_num1 &  op_num2
         # !op_num0 &  op_num2
         #  _LC1_A3 &  op_num0 &  op_num1 & !op_num2
         # !_LC1_A3 &  op_num2;

-- Node name is ':556' 
-- Equation name is '_LC3_A6', type is buried 
_LC3_A6  = LCELL( _EQ055);
  _EQ055 = !op_num0 &  op_num1
         #  _LC1_A3 &  op_num0 & !op_num1
         # !_LC1_A3 &  op_num1;

-- Node name is ':604' 
-- Equation name is '_LC6_A8', type is buried 
!_LC6_A8 = _LC6_A8~NOT;
_LC6_A8~NOT = LCELL( _EQ056);
  _EQ056 = !ch_num6 &  op_num6
         # !ch_num6 & !_LC5_A8
         # !_LC5_A8 &  op_num6;

-- Node name is ':609' 
-- Equation name is '_LC5_A8', type is buried 
!_LC5_A8 = _LC5_A8~NOT;
_LC5_A8~NOT = LCELL( _EQ057);
  _EQ057 = !ch_num5 &  op_num5
         # !ch_num5 & !_LC4_A8
         # !_LC4_A8 &  op_num5;

-- Node name is ':614' 
-- Equation name is '_LC4_A8', type is buried 
!_LC4_A8 = _LC4_A8~NOT;
_LC4_A8~NOT = LCELL( _EQ058);
  _EQ058 = !ch_num4 &  op_num4
         # !ch_num4 & !_LC3_A8
         # !_LC3_A8 &  op_num4;

-- Node name is ':619' 
-- Equation name is '_LC3_A8', type is buried 
!_LC3_A8 = _LC3_A8~NOT;
_LC3_A8~NOT = LCELL( _EQ059);
  _EQ059 = !ch_num3 &  op_num3
         # !ch_num3 & !_LC4_A6
         # !_LC4_A6 &  op_num3;

-- Node name is ':624' 
-- Equation name is '_LC4_A6', type is buried 
!_LC4_A6 = _LC4_A6~NOT;
_LC4_A6~NOT = LCELL( _EQ060);
  _EQ060 = !ch_num2 &  op_num2
         # !ch_num2 & !_LC8_A6
         # !_LC8_A6 &  op_num2;

-- Node name is ':629' 
-- Equation name is '_LC8_A6', type is buried 
!_LC8_A6 = _LC8_A6~NOT;
_LC8_A6~NOT = LCELL( _EQ061);
  _EQ061 = !ch_num1 &  op_num1
         # !ch_num0 & !ch_num1
         # !ch_num0 &  op_num1
         # !ch_num1 &  op_num0
         #  op_num0 &  op_num1;

-- Node name is '~637~1' 
-- Equation name is '~637~1', location is LC8_A8, type is buried.
-- synthesized logic cell 
_LC8_A8  = LCELL( _EQ062);
  _EQ062 = !ch_num7 &  op_num7
         # !ch_num7 & !_LC6_A8
         # !_LC6_A8 &  op_num7;

-- Node name is ':643' 
-- Equation name is '_LC7_A3', type is buried 
_LC7_A3  = DFFE( _EQ063, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ063 =  data_cycle &  _LC7_A3
         #  data_cycle &  _LC8_A8 &  op_active;

-- Node name is ':647' 
-- Equation name is '_LC6_A3', type is buried 
_LC6_A3  = DFFE( _EQ064, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ064 = !_LC7_A3 &  op_active;

-- Node name is ':648' 
-- Equation name is '_LC2_A3', type is buried 
_LC2_A3  = LCELL( _EQ065);
  _EQ065 =  data_cycle &  _LC6_A3;

-- Node name is ':661' 
-- Equation name is '_LC1_B3', type is buried 
!_LC1_B3 = _LC1_B3~NOT;
_LC1_B3~NOT = DFFE( _EQ066, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ066 =  fresh_cycle &  _LC7_B7
         #  _LC7_B7 &  load_cycle
         #  _LC2_A3;

-- Node name is '~677~1' 
-- Equation name is '~677~1', location is LC4_B3, type is buried.
-- synthesized logic cell 
!_LC4_B3 = _LC4_B3~NOT;
_LC4_B3~NOT = LCELL( _EQ067);
  _EQ067 =  load_cycle
         #  charge_cycle;

-- Node name is ':680' 
-- Equation name is '_LC6_B3', type is buried 
!_LC6_B3 = _LC6_B3~NOT;
_LC6_B3~NOT = DFFE( _EQ068, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ068 = !_LC4_B3 &  _LC7_B7
         #  _LC2_A3 & !wr_l;

-- Node name is ':682' 
-- Equation name is '_LC1_C19', type is buried 
_LC1_C19 = DFFE( VCC, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);

-- Node name is ':736' 
-- Equation name is '_LC8_C18', type is buried 
_LC8_C18 = DFFE( _EQ069, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ069 =  byte_en15 &  _LC2_A3 & !wr_l;

-- Node name is ':737' 
-- Equation name is '_LC8_C15', type is buried 
_LC8_C15 = DFFE( _EQ070, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ070 =  byte_en14 &  _LC2_A3 & !wr_l;

-- Node name is ':738' 
-- Equation name is '_LC7_C15', type is buried 
_LC7_C15 = DFFE( _EQ071, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ071 =  byte_en13 &  _LC2_A3 & !wr_l;

-- Node name is ':739' 
-- Equation name is '_LC5_C18', type is buried 
_LC5_C18 = DFFE( _EQ072, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ072 =  byte_en12 &  _LC2_A3 & !wr_l;

-- Node name is ':740' 
-- Equation name is '_LC6_C15', type is buried 
_LC6_C15 = DFFE( _EQ073, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ073 =  byte_en11 &  _LC2_A3 & !wr_l;

-- Node name is ':741' 
-- Equation name is '_LC4_C18', type is buried 
_LC4_C18 = DFFE( _EQ074, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ074 =  byte_en10 &  _LC2_A3 & !wr_l;

-- Node name is ':742' 
-- Equation name is '_LC7_C18', type is buried 
_LC7_C18 = DFFE( _EQ075, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ075 =  byte_en9 &  _LC2_A3 & !wr_l;

-- Node name is ':743' 
-- Equation name is '_LC5_C15', type is buried 
_LC5_C15 = DFFE( _EQ076, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ076 =  byte_en8 &  _LC2_A3 & !wr_l;

-- Node name is ':744' 
-- Equation name is '_LC3_C15', type is buried 
_LC3_C15 = DFFE( _EQ077, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ077 =  byte_en7 &  _LC2_A3 & !wr_l;

-- Node name is ':745' 
-- Equation name is '_LC1_C15', type is buried 
_LC1_C15 = DFFE( _EQ078, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ078 =  byte_en6 &  _LC2_A3 & !wr_l;

-- Node name is ':746' 
-- Equation name is '_LC2_C18', type is buried 
_LC2_C18 = DFFE( _EQ079, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ079 =  byte_en5 &  _LC2_A3 & !wr_l;

-- Node name is ':747' 
-- Equation name is '_LC1_C18', type is buried 
_LC1_C18 = DFFE( _EQ080, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ080 =  byte_en4 &  _LC2_A3 & !wr_l;

-- Node name is ':748' 
-- Equation name is '_LC2_C15', type is buried 
_LC2_C15 = DFFE( _EQ081, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ081 =  byte_en3 &  _LC2_A3 & !wr_l;

-- Node name is ':749' 
-- Equation name is '_LC6_C18', type is buried 
_LC6_C18 = DFFE( _EQ082, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ082 =  byte_en2 &  _LC2_A3 & !wr_l;

-- Node name is ':750' 
-- Equation name is '_LC3_C18', type is buried 
_LC3_C18 = DFFE( _EQ083, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ083 =  byte_en1 &  _LC2_A3 & !wr_l;

-- Node name is ':751' 
-- Equation name is '_LC4_C15', type is buried 
_LC4_C15 = DFFE( _EQ084, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);
  _EQ084 =  byte_en0 &  _LC2_A3 & !wr_l;

-- Node name is ':757' 
-- Equation name is '_LC4_B11', type is buried 
!_LC4_B11 = _LC4_B11~NOT;
_LC4_B11~NOT = DFFE( data_cycle, GLOBAL( clk), GLOBAL( rst_l),  VCC,  VCC);



Project Information                                     d:\newsdram\sd_sig.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 67,261K