偽隨機序列發(fā)生器的vhdl算法
設(shè)計一個偽隨機序列發(fā)生器，采用的生成多項式為1+X^3+X^7。要求具有一個RESET端和兩個控制端來調(diào)整寄存器初值（程序中設(shè)定好四種非零初值可選）。

補充 - 11個月前
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

-- Uncomment the following lines to use the declarations that are 
-- provided for instantiating Xilinx primitive components. 
--library UNISIM; 
--use UNISIM.VComponents.all; 

entity wsjxl is 
Port (CLK,OE,RESET:in std_logic; 
SEL:in std_logic_vector(1 downto 0); 
DOUT:out std_logic_vector(7 downto 0)); 
end wsjxl; 

architecture Behavioral of wsjxl is 
signal ddout:std_logic_vector(7 downto 0); 
signal a,b:std_logic; 
begin 
process(CLK,SEL,OE,RESET) 
begin 

if(RESET='1' or (RESET='0' and OE='0'))then 

ddout<="00000000"; 
elsif(RESET='0' and OE='1')then 
case SEL is 
when"00"=>ddout<="00011001"; 
when"01"=>ddout<="00010001"; 
when"10"=>ddout<="00001001"; 
when others=>ddout<="01111001"; 
end case; 
if(CLK'EVENT and CLK='1')then 

ddout(0) <= ddout(0) xor ddout(3) xor ddout(7); 
ddout(7 downto 1)<=ddout(6 downto 0); 
end if; 
end if; 
DOUT<=ddout; 
end process; 
end Behavioral;