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<title>USING THE VIDEO INPUT PORT ON THE XST-3.0 BOARD</title>
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<li><a href="#using_the_video_input_port_on_the_xst3_0_board">USING THE VIDEO INPUT PORT ON THE XST-3.0 BOARD</a></li>
<li><a href="#design_files">DESIGN FILES</a></li>
<li><a href="#using_the_design_example">USING THE DESIGN EXAMPLE</a></li>
<li><a href="#environment">ENVIRONMENT</a></li>
<li><a href="#source_files">SOURCE FILES</a></li>
<li><a href="#author">AUTHOR</a></li>
<li><a href="#copyright_and_license">COPYRIGHT AND LICENSE</a></li>
<li><a href="#history">HISTORY</a></li>
</ul>
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<h1><a name="using_the_video_input_port_on_the_xst3_0_board">USING THE VIDEO INPUT PORT ON THE XST-3.0 BOARD</a></h1>
<p>This is a simple design to grab frames of video data and display them on a VGA monitor.</p>
<p>
</p>
<hr />
<h1><a name="design_files">DESIGN FILES</a></h1>
<ul>
<li><strong><a name="item_common_2evhd"><em>common.vhd</em></a></strong><br />
</li>
This file contains some definitions and functions used in the rest of the VHDL code.
<p></p>
<li><strong><a name="item_sdramcntl_2evhd"><em>sdramcntl.vhd</em></a></strong><br />
</li>
This VHDL file describes a controller that simplifies writing/reading data to/from an SDRAM.
<p></p>
<li><strong><a name="item_xsasdramcntl_2evhd"><em>xsasdramcntl.vhd</em></a></strong><br />
</li>
This VHDL file surrounds the generic SDRAM controller with a wrapper that customizes it for the XSA Boards.
<p></p>
<li><strong><a name="item_fifo_2evhd"><em>fifo.vhd</em></a></strong><br />
</li>
This file contains concise VHDL descriptions of the synchronous and asynchronous FIFOs
described in Xilinx application note XAPP131.
<p></p>
<li><strong><a name="item_framegrabber_2evhd"><em>framegrabber.vhd</em></a></strong><br />
</li>
This VHDL file describes a simple state machine that accepts pixels from a video decoder and places them
in a FIFO buffer.
<p></p>
<li><strong><a name="item_vga_2evhd"><em>vga.vhd</em></a></strong><br />
</li>
This VHDL file describes a controller that accepts a stream of pixels and displays them on a VGA monitor.
<p></p>
<li><strong><a name="item_video_2evhd"><em>video.vhd</em></a></strong><br />
</li>
This VHDL file ties the previous modules together to form a complete frame grabber application.
When a button is pressed, the video codec dumps a stream of pixels in ITU-R BT.656 format,
8-bit 4:2:2 with embedded syncs to the framegrabber module using a sampling clock of 27 MHz.
The framegrabber loads the pixels into a FIFO (along with some framing information).
A finite-state machine (FSM) offloads the pixels from the FIFO at 50 MHz and stores the
pixels into SDRAM while interleaving the lines of video from the odd and even fields.
Another address counter is used to read stored pixels from the SDRAM at 50 MHz and load them
into a FIFO. The VGA generator retrieves pixels from this FIFO and displays them on a monitor.
<tt>
<table>
<span class="c1">__________ <br/>
| | </span><span class="c2">_________ </span><span class="c1">______________ <br/>
| Parallel | </span><span class="c2">| | </span><span class="c1">| | __________ <br/>
| Port | </span><span class="c2">| Button | </span><span class="c1">| Address Cntr | | | <br/>
|__________| </span><span class="c2">|_________| </span><span class="c1">| + FSM |--->| | <br/>
| </span><span class="c2">| </span><span class="c1">|______________| | | <br/>
| </span><span class="c2">| </span><span class="c1">| | <br/>
____V____ ____</span><span class="c2">V</span><span class="c1">____ ______________ | | ____________ _______ <br/>
| | | | | | | | | | | |<br/>
| Video |--->| Frame |--->| FIFO |--->| | | | | |<br/>
| Codec | | Grabber | |_</span><span class="c2">__</span><span class="c1">___________| | | | | | |<br/>
|_________| |_________| | | | SDRAM | | |<br/>
| Dualport |<--->| Controller |<--->| SDRAM |<br/>
_________ _________ ______________ | | | | | |<br/>
| | | | | | | | | | | |<br/>
| Monitor |<---| VGA |<---| </span><span class="c2">FIFO </span><span class="c1">|<---| | | | | |<br/>
|_________| |_________| |______________| | | |____________| |_______|<br/>
| | <br/>
______________ | | <br/>
| | | | <br/>
| Address Cntr |--->| | <br/>
|______________| |__________| <br/>
</span>
</table>
</tt>
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