#
# Pin assignments for the XSA-3S1000 Board.
#

net clk_in       loc=T9;  # 100 MHz clock signal
net grab_frame_n loc=H4;  # pushbutton PB1

# video decoder interface
net vidin_clk    loc=H16; # clock from the video decoder 
net vidin_y<0>   loc=H14; # pixel data (least-significant bit)
net vidin_y<1>   loc=M4;  
net vidin_y<2>   loc=P1;  
net vidin_y<3>   loc=N3;  
net vidin_y<4>   loc=M15; 
net vidin_y<5>   loc=H13; 
net vidin_y<6>   loc=G16; 
net vidin_y<7>   loc=N15; # pixel data (most-significant bit) 

# bargraph LED
net status<0>    loc=L5;  # segment 1  
net status<1>    loc=N2;  # segment 2
net status<2>    loc=M3;  # segment 3
net status<3>    loc=N1;  # segment 4
net status<4>    loc=T13; # segment 5
net status<5>    loc=L15; # segment 6
net status<6>    loc=J13; # segment 7
net status<7>    loc=H15; # segment 8

# VGA monitor interface
net r<0>         loc=C8;  # red (least-significant bit)  
net r<1>         loc=D6;  
net r<2>         loc=B1;  # red (most-significant bit)
net g<0>         loc=A8;  # green (least-significant bit)
net g<1>         loc=A5;  
net g<2>         loc=C3;  # green (most-significant bit)
net b<0>         loc=C9;  # blue (least-significant bit)
net b<1>         loc=E7;  
net b<2>         loc=D5;  # blue (most-significant bit)
net hsync_n      loc=B7;  # horizontal sync
net vsync_n      loc=D8;  # vertical sync

# SDRAM	interface
net sclkfb       loc=N8;  # SDRAM clock fed back into the FPGA  
net sclk         loc=E10; # clock from FPGA to SDRAM 
net cke          loc=D7;  # clock-enable
net cs_n         loc=B8;  # chip-select
net ras_n        loc=A9;  # RAS
net cas_n        loc=A10; # CAS
net we_n         loc=B10; # write-enable
net ba<0>        loc=A7;  # bank address 0
net ba<1>        loc=C7;  # bank address 1
net sAddr<0>     loc=B5;  # row/column address 0 (least-significant bit)
net sAddr<1>     loc=A4;  
net sAddr<2>     loc=B4;  
net sAddr<3>     loc=E6;  
net sAddr<4>     loc=E3;  
net sAddr<5>     loc=C1;  
net sAddr<6>     loc=E4;  
net sAddr<7>     loc=D3;  
net sAddr<8>     loc=C2;  
net sAddr<9>     loc=A3;  
net sAddr<10>    loc=B6;  
net sAddr<11>    loc=C5;  
net sAddr<12>    loc=C6;  # row/column address 12 (most-significant bit)  
net sData<0>     loc=C15; # data bit 0 (least-significant bit)
net sData<1>     loc=D12; 
net sData<2>     loc=A14; 
net sData<3>     loc=B13; 
net sData<4>     loc=D11; 
net sData<5>     loc=A12; 
net sData<6>     loc=C11; 
net sData<7>     loc=D10; 
net sData<8>     loc=B11; 
net sData<9>     loc=B12; 
net sData<10>    loc=C12; 
net sData<11>    loc=B14; 
net sData<12>    loc=D14; 
net sData<13>    loc=C16; 
net sData<14>    loc=F12; 
net sData<15>    loc=F13; # data bit 15 (most-significant bit) 
net dqmh         loc=D9;  # qualifier for upper-byte of data bus
net dqml         loc=C10; # qualifier for lower byte of data bus

# PC-to-video decoder I2C interface (thru the CPLD)
net lp_d<0>      loc=N14; # data bit D0 
net lp_d<1>      loc=P15; # data bit D1
net lp_s<3>      loc=N5;  # status bit S3
net lp_s<4>      loc=K14; # status bit S4
net scl          loc=F5;  # I2C clock
net sda          loc=D2;  # I2C data to video decoder