module pd6 ( In_0 , In_1 , Out_0 , Out_1 ) ;

input  In_0 ,  In_1 ;
output Out_0 , Out_1 ;

reg    T_F_0 , T_F_1 ;
wire   T_U;


always @( negedge In_0 or posedge T_U )
  if ( T_U )
    T_F_0 = 1'b0 ;
  else
    T_F_0 = 1'b1 ;


always @( negedge In_1 or posedge T_U )
  if ( T_U )
    T_F_1 = 1'b0 ;
  else
    T_F_1 = 1'b1 ;


assign T_U = T_F_0 & T_F_1 ;


assign Out_0 = T_F_0 & ( ~ T_F_1 ) ;
assign Out_1 = ( ~ T_F_0 ) & T_F_1 ;


endmodule