# TCL File Generated by Component Editor 7.2sp1 on:# Fri Feb 15 14:49:25 MST 2008# DO NOT MODIFYset_source_file "eth_ocm.v"set_module "eth_ocm"set_module_description "OpenCores 10/100 Mac with Avalon Interface"set_module_property "Is_Ethernet_Mac" "1"set_module_property "author" "Jakob Jones"set_module_property "className" "eth_ocm"set_module_property "displayName" "OpenCores 10/100 MAC"set_module_property "group" "Interface Protocols/Ethernet"set_module_property "instantiateInSystemModule" "true"set_module_property "synthesisFiles" [ list "eth_ocm.v" "C:/Projects/JEP/X6/jep_ocm/src/sopc/eth_ocm/eth_ocm.v" ]# Module parametersadd_parameter "TOTAL_DESCRIPTORS" "integer" "128" "Number of descriptors"add_parameter "TX_FIFO_SIZE_IN_BYTES" "integer" "128" "Size of TX FIFO (in bytes)"add_parameter "RX_FIFO_SIZE_IN_BYTES" "integer" "4096" "Size of RX FIFO (in bytes)"# Interface clock_sinkadd_interface "clock_sink" "clock" "sink" "asynchronous"# Ports in interface clock_sinkadd_port_to_interface "clock_sink" "av_clk" "clk"add_port_to_interface "clock_sink" "av_reset" "reset"# Interface control_portadd_interface "control_port" "avalon" "slave" "clock_sink"set_interface_property "control_port" "isNonVolatileStorage" "false"set_interface_property "control_port" "burstOnBurstBoundariesOnly" "false"set_interface_property "control_port" "readLatency" "0"set_interface_property "control_port" "readWaitStates" "0"set_interface_property "control_port" "holdTime" "0"set_interface_property "control_port" "printableDevice" "false"set_interface_property "control_port" "readWaitTime" "0"set_interface_property "control_port" "setupTime" "0"set_interface_property "control_port" "addressAlignment" "NATIVE"set_interface_property "control_port" "writeWaitTime" "0"set_interface_property "control_port" "timingUnits" "Cycles"set_interface_property "control_port" "minimumUninterruptedRunLength" "1"set_interface_property "control_port" "isMemoryDevice" "false"set_interface_property "control_port" "linewrapBursts" "false"set_interface_property "control_port" "maximumPendingReadTransactions" "0"# Ports in interface control_portadd_port_to_interface "control_port" "av_address" "address"add_port_to_interface "control_port" "av_write" "write"add_port_to_interface "control_port" "av_read" "read"add_port_to_interface "control_port" "av_writedata" "writedata"add_port_to_interface "control_port" "av_readdata" "readdata"add_port_to_interface "control_port" "av_waitrequest_n" "waitrequest_n"add_port_to_interface "control_port" "av_chipselect" "chipselect"# Interface rx_masteradd_interface "rx_master" "avalon" "master" "clock_sink"set_interface_property "rx_master" "burstOnBurstBoundariesOnly" "false"set_interface_property "rx_master" "doStreamReads" "false"set_interface_property "rx_master" "linewrapBursts" "false"set_interface_property "rx_master" "doStreamWrites" "false"# Ports in interface rx_masteradd_port_to_interface "rx_master" "av_rx_waitrequest" "waitrequest"add_port_to_interface "rx_master" "av_rx_address" "address"add_port_to_interface "rx_master" "av_rx_write" "write"add_port_to_interface "rx_master" "av_rx_writedata" "writedata"add_port_to_interface "rx_master" "av_rx_byteenable" "byteenable"# Interface tx_masteradd_interface "tx_master" "avalon" "master" "clock_sink"set_interface_property "tx_master" "burstOnBurstBoundariesOnly" "false"set_interface_property "tx_master" "doStreamReads" "false"set_interface_property "tx_master" "linewrapBursts" "false"set_interface_property "tx_master" "doStreamWrites" "false"# Ports in interface tx_masteradd_port_to_interface "tx_master" "av_tx_readdata" "readdata"add_port_to_interface "tx_master" "av_tx_waitrequest" "waitrequest"add_port_to_interface "tx_master" "av_tx_readdatavalid" "readdatavalid"add_port_to_interface "tx_master" "av_tx_address" "address"add_port_to_interface "tx_master" "av_tx_read" "read"# Interface MII_Conduitadd_interface "MII_Conduit" "conduit" "start" "asynchronous"# Ports in interface MII_Conduitadd_port_to_interface "MII_Conduit" "mtx_clk_pad_i" "export"add_port_to_interface "MII_Conduit" "mtxd_pad_o" "export"add_port_to_interface "MII_Conduit" "mtxen_pad_o" "export"add_port_to_interface "MII_Conduit" "mtxerr_pad_o" "export"add_port_to_interface "MII_Conduit" "mrx_clk_pad_i" "export"add_port_to_interface "MII_Conduit" "mrxd_pad_i" "export"add_port_to_interface "MII_Conduit" "mrxdv_pad_i" "export"add_port_to_interface "MII_Conduit" "mrxerr_pad_i" "export"add_port_to_interface "MII_Conduit" "mcoll_pad_i" "export"add_port_to_interface "MII_Conduit" "mcrs_pad_i" "export"add_port_to_interface "MII_Conduit" "mdc_pad_o" "export"add_port_to_interface "MII_Conduit" "md_pad_i" "export"add_port_to_interface "MII_Conduit" "md_pad_o" "export"add_port_to_interface "MII_Conduit" "md_padoe_o" "export"# Interface interrupt_senderadd_interface "interrupt_sender" "interrupt" "sender" "clock_sink"set_interface_property "interrupt_sender" "associatedAddressablePoint" "control_port"# Ports in interface interrupt_senderadd_port_to_interface "interrupt_sender" "av_irq" "irq"