//////////////////////////////////////////////////////////////////////////                                                              ////////  eth_avalon.v                                                ////////                                                              ////////  This file is a patch used in conjunction with the           ////////  Ethernet IP core project.                                   ////////  http://www.opencores.org/projects/ethmac/                   ////////                                                              ////////  Author(s):                                                  ////////      - Jakob Jones (jrjonsie@gmail.com)                      ////////                                                              ////////  All additional information is available in the Readme.txt   ////////  file.                                                       ////////                                                              //////////////////////////////////////////////////////////////////////////`include "eth_defines.v"`include "timescale.v"// Parameter DESC_COUNT is the number of descriptors to use.// Parameter RX_FIFO_DEPTH is the Depth of the Receive FIFO (in bytes)// Parameter TX_FIFO_DEPTH is the Depth of the Transmit FIFO (in bytes)module eth_avalon   #(  parameter   DESC_COUNT      = 128,                        parameter   RX_FIFO_DEPTH   = 4096,                        parameter   TX_FIFO_DEPTH   = 128   ) (    input                   av_reset,           //Asynchronous reset (Avalon side)    input                   av_clk,             //Avalon clock    //Avalon Control Port     //inputs    input                   av_cs,              //Avalon slave BD chipselect    input                   av_write,           //Avalon slave write    input                   av_read,            //Avalon slave read    input       [7:0]       av_address,         //Avalon slave address    input       [31:0]      av_writedata,       //Avalon slave writedata      //outputs    output      [31:0]      av_readdata,        //Avalon slave readdata    output                  av_waitrequest_n,   //Avalon slave waitrequest    //Avalon TX memory port      //input    input                   av_tx_waitrequest,  //Avalon TX master waitrequest    input                   av_tx_readdatavalid,//Avalon TX master readdatavalid    input       [31:0]      av_tx_readdata,     //Avalon TX master readdata      //output    output      [31:0]      av_tx_address,      //Avalon TX master address    output                  av_tx_read,         //Avalon TX master read    //Avalon RX memory port      //inputs    input                   av_rx_waitrequest,  //Avalon RX master waitrequest      //outputs    output      [31:0]      av_rx_address,      //Avalon RX master address    output                  av_rx_write,        //Avalon RX master write    output      [31:0]      av_rx_writedata,    //Avalon RX master writedata    output      [3:0]       av_rx_byteenable,   //Avalon RX master byteenable    // Rx Status signals    input                   InvalidSymbol,      // Invalid symbol was received during reception in 100 Mbps mode    input                   LatchedCrcError,    // CRC error    input                   RxLateCollision,    // Late collision occured while receiving frame    input                   ShortFrame,         // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)    input                   DribbleNibble,      // Extra nibble received    input                   ReceivedPacketTooBig,// Received packet is bigger than r_MaxFL    input        [15:0]     RxLength,           // Length of the incoming frame    input                   LoadRxStatus,       // Rx status was loaded    input                   ReceivedPacketGood, // Received packet's length and CRC are good    input                   AddressMiss,        // When a packet is received AddressMiss status is written to the Rx BD    input                   r_RxFlow,           /*TODO*/    input                   r_PassAll,          /*TODO*/    input                   ReceivedPauseFrm,   /*TODO*/        // Tx Status signals    input       [3:0]       RetryCntLatched,    // Latched Retry Counter    input                   RetryLimit,         // Retry limit reached (Retry Max value + 1 attempts were made)    input                   LateCollLatched,    // Late collision occured    input                   DeferLatched,       // Defer indication (Frame was defered before sucessfully sent)    output                  RstDeferLatched,    // Ack DeferLatched    input                   CarrierSenseLost,   // Carrier Sense was lost during the frame transmission        // Tx    input                   MTxClk,             // Transmit clock (from PHY)    input                   TxUsedData,         // Transmit packet used data (this is an ack)    input                   TxRetry,            // Transmit packet retry    input                   TxAbort,            // Transmit packet abort    input                   TxDone,             // Transmission ended    output                  TxStartFrm,         // Transmit packet start frame    output                  TxEndFrm,           // Transmit packet end frame    output      [7:0]       TxData,             // Transmit packet data byte    output                  TxUnderRun,         // Transmit packet under-run    output                  PerPacketCrcEn,     // Per packet crc enable    output                  PerPacketPad,       // Per packet pading        // Rx    input                   MRxClk,             // Receive clock (from PHY)    input       [7:0]       RxData,             // Received data byte    input                   RxValid,            // Receive data valid    input                   RxStartFrm,         // Receive start of frame    input                   RxEndFrm,           // Receive end of frame    input                   RxAbort,            // This signal is set when address doesn't match.    output  reg             RxStatusWriteLatched_sync2, //indication back         //Register    input                   r_TxEn,             // Transmit enable    input                   r_RxEn,             // Receive enable    input       [7:0]       r_TxBDNum,          // Receive buffer descriptor number        // Interrupts    output                  TxB_IRQ,            // Transmit successful IRQ    output                  TxE_IRQ,            // Transmit error IRQ    output                  RxB_IRQ,            // Receive successful IRQ    output                  RxE_IRQ,            // Receive error IRQ    output                  Busy_IRQ            // Receive busy IRQ            // Bist    `ifdef ETH_BIST    ,    input                   mbist_si_i,       // bist scan serial in    output                  mbist_so_o,       // bist scan serial out    input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i    // bist chain shift control    `endif    );//Some useful constant functions`include "eth_avalon_functions.v"localparam  Tp = 1;//Determine the numberlocalparam  RDC = min(max(nextPow2(DESC_COUNT), 2), 128);   //Real descriptor count localparam  MAX_DESC = RDC - 1;     //highest index descriptor//Avalon interface signalswire            av_waitrequest;     // Avalon slave waitrequestwire            av_bd_desc_cs;      // Avalon Descriptor RAM is selectedwire    [31:0]  av_desc_readdata;   // Avalon Descriptor readback datawire            av_bd_ptr_cs;       // Avalon Pointer RAM is selectedwire    [31:0]  av_ptr_readdata;    // Avalon Pointer readback datareg             av_read_r;          // Avalon read registered//Descriptor interface signalswire    [7:0]   max_rx_bd;          // Highest RX descriptor index//RX BD interfacewire            rx_bd_wait;         // RX BD wait signalwire            rx_bd_write;        // RX BD write signalwire            rx_bd_read;         // RX BD read signalreg             rx_bd_read_r;       // RX BD read registered (used for wait)wire    [6:0]   rx_bd_index;        // RX BD descriptor or pointer indexwire    [31:0]  rx_bd_writedata;    // RX BD descriptor writeback data//TX BD interfacewire            tx_bd_wait;         // TX BD wait signalwire            tx_bd_write;        // TX BD write signalwire            tx_bd_read;         // TX BD read signalreg             tx_bd_read_r;       // TX BD read registered (used for wait)wire    [6:0]   tx_bd_index;        // TX BD descriptor or pointer indexwire    [31:0]  tx_bd_writedata;    // TX BD descriptor writeback data//Muxed BD interfacewire    [31:0]  bd_desc;            // Descriptor data from BD RAM wire    [31:0]  bd_ptr;             // Pointer data from BD RAMwire            bd_write;           // Descriptor data write to BD RAMwire    [6:0]   bd_index;           // Descriptor/Pointer index to BD RAMwire    [31:0]  bd_writedata;       // Descriptor writeback data to BD RAMreg             rx_txn_sel;         // 1 = MUX RX to BD RAM, 0 = MUX TX//Receive side signalsreg             rx_reset;           // Reset Receive interfacewire    [8:0]   RxStatus;           // RX Status from MAC corereg     [8:0]   RxStatus_r;         // RX Status latched//Transmit side signalsreg             tx_reset;           // Reset Transmit interfacereg             Flop;               // Follow nomenclature from eth_wishbone                                    // toggles to activate TxUsedDatareg             TxUnderRun_r;       // Underrun of TX FIFO reg             tx_retry;           // TX retry signalwire            tx_stat_ack;        // TX status ack`ifdef ETH_BISTassign  mbist_so_o = mbist_si_i;`endifassign  av_waitrequest_n    = ~av_waitrequest;//***************************************************************************//************************** Descriptor Interface ***************************// Avalon bus is in wait if:// 1 - The BD RAM is not selected// 2 - The Avalon BUS issued a read but data is not available yetassign  av_waitrequest  = (~av_cs) | (av_read & ~av_read_r);// Select pointer RAM or descriptor RAM based on lowest address bitassign  av_bd_ptr_cs    = av_address[0];assign  av_bd_desc_cs   = ~av_address[0];// Mux Pointer or descriptor readback data to Avalon BUSassign  av_readdata     = av_bd_ptr_cs? av_ptr_readdata: av_desc_readdata;// Mux TX or RX address, data, and control signalsassign  bd_write    = rx_txn_sel ? rx_bd_write              : tx_bd_write;assign  bd_writedata= rx_txn_sel ? rx_bd_writedata          : tx_bd_writedata;