.Clk       (Clk),   .Reset     (Reset),   .SyncReset (1'b0)  );eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2)          RXHASH1_2  (   .DataIn    (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),   .Write     (HASH1_Wr[2]),   .Clk       (Clk),   .Reset     (Reset),   .SyncReset (1'b0)  );eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3)          RXHASH1_3  (   .DataIn    (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),   .DataOut   (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),   .Write     (HASH1_Wr[3]),   .Clk       (Clk),   .Reset     (Reset),   .SyncReset (1'b0)  );// TXCTRL Registereth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0)  TXCTRL_0  (   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),   .Write     (TXCTRL_Wr[0]),   .Clk       (Clk),   .Reset     (Reset),   .SyncReset (1'b0)  );eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1)  TXCTRL_1  (   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),   .Write     (TXCTRL_Wr[1]),   .Clk       (Clk),   .Reset     (Reset),   .SyncReset (1'b0)  );eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2)  TXCTRL_2 // Request bit is synchronously reset  (   .DataIn    (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),   .DataOut   (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),   .Write     (TXCTRL_Wr[2]),   .Clk       (Clk),   .Reset     (Reset),   .SyncReset (RstTxPauseRq)  );assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;// Reading data from registersalways @ (Address       or Read           or MODEROut       or INT_SOURCEOut  or          INT_MASKOut   or IPGTOut        or IPGR1Out       or IPGR2Out       or          PACKETLENOut  or COLLCONFOut    or CTRLMODEROut   or MIIMODEROut    or          MIICOMMANDOut or MIIADDRESSOut  or MIITX_DATAOut  or MIIRX_DATAOut  or           MIISTATUSOut  or MAC_ADDR0Out   or MAC_ADDR1Out   or TX_BD_NUMOut   or          HASH0Out      or HASH1Out       or TXCTRLOut                )begin  if(Read)  // read    begin      case(Address)        `ETH_MODER_ADR        :  DataOut<=MODEROut;        `ETH_INT_SOURCE_ADR   :  DataOut<=INT_SOURCEOut;        `ETH_INT_MASK_ADR     :  DataOut<=INT_MASKOut;        `ETH_IPGT_ADR         :  DataOut<=IPGTOut;        `ETH_IPGR1_ADR        :  DataOut<=IPGR1Out;        `ETH_IPGR2_ADR        :  DataOut<=IPGR2Out;        `ETH_PACKETLEN_ADR    :  DataOut<=PACKETLENOut;        `ETH_COLLCONF_ADR     :  DataOut<=COLLCONFOut;        `ETH_CTRLMODER_ADR    :  DataOut<=CTRLMODEROut;        `ETH_MIIMODER_ADR     :  DataOut<=MIIMODEROut;        `ETH_MIICOMMAND_ADR   :  DataOut<=MIICOMMANDOut;        `ETH_MIIADDRESS_ADR   :  DataOut<=MIIADDRESSOut;        `ETH_MIITX_DATA_ADR   :  DataOut<=MIITX_DATAOut;        `ETH_MIIRX_DATA_ADR   :  DataOut<=MIIRX_DATAOut;        `ETH_MIISTATUS_ADR    :  DataOut<=MIISTATUSOut;        `ETH_MAC_ADDR0_ADR    :  DataOut<=MAC_ADDR0Out;        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;        `ETH_TX_CTRL_ADR      :  DataOut<=TXCTRLOut;        default:             DataOut<=32'h0;      endcase    end  else    DataOut<=32'h0;endassign r_RecSmall         = MODEROut[16];assign r_Pad              = MODEROut[15];assign r_HugEn            = MODEROut[14];assign r_CrcEn            = MODEROut[13];assign r_DlyCrcEn         = MODEROut[12];// assign r_Rst           = MODEROut[11];   This signal is not used any moreassign r_FullD            = MODEROut[10];assign r_ExDfrEn          = MODEROut[9];assign r_NoBckof          = MODEROut[8];assign r_LoopBck          = MODEROut[7];assign r_IFG              = MODEROut[6];assign r_Pro              = MODEROut[5];assign r_Iam              = MODEROut[4];assign r_Bro              = MODEROut[3];assign r_NoPre            = MODEROut[2];assign r_TxEn             = MODEROut[1] & (TX_BD_NUMOut>0);     // Transmission is enabled when there is at least one TxBD.assign r_RxEn             = MODEROut[0] & (TX_BD_NUMOut<'h80);  // Reception is enabled when there is  at least one RxBD.assign r_IPGT[6:0]        = IPGTOut[6:0];assign r_IPGR1[6:0]       = IPGR1Out[6:0];assign r_IPGR2[6:0]       = IPGR2Out[6:0];assign r_MinFL[15:0]      = PACKETLENOut[31:16];assign r_MaxFL[15:0]      = PACKETLENOut[15:0];assign r_MaxRet[3:0]      = COLLCONFOut[19:16];assign r_CollValid[5:0]   = COLLCONFOut[5:0];assign r_TxFlow           = CTRLMODEROut[2];assign r_RxFlow           = CTRLMODEROut[1];assign r_PassAll          = CTRLMODEROut[0];assign r_MiiNoPre         = MIIMODEROut[8];assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];assign r_WCtrlData        = MIICOMMANDOut[2];assign r_RStat            = MIICOMMANDOut[1];assign r_ScanStat         = MIICOMMANDOut[0];assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0; assign MIISTATUSOut[2]    = NValid_stat         ; assign MIISTATUSOut[1]    = Busy_stat           ; assign MIISTATUSOut[0]    = LinkFail            ; assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];assign r_HASH1[31:0]      = HASH1Out;assign r_HASH0[31:0]      = HASH0Out;assign r_TxBDNum[7:0]     = TX_BD_NUMOut[7:0];assign r_TxPauseTV[15:0]  = TXCTRLOut[15:0];assign r_TxPauseRq        = TXCTRLOut[16];// Synchronizing TxC Interruptalways @ (posedge TxClk or posedge Reset)begin  if(Reset)    SetTxCIrq_txclk <=#Tp 1'b0;  else  if(TxCtrlEndFrm & StartTxDone & r_TxFlow)    SetTxCIrq_txclk <=#Tp 1'b1;  else  if(ResetTxCIrq_sync2)    SetTxCIrq_txclk <=#Tp 1'b0;endalways @ (posedge Clk or posedge Reset)begin  if(Reset)    SetTxCIrq_sync1 <=#Tp 1'b0;  else    SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk;endalways @ (posedge Clk or posedge Reset)begin  if(Reset)    SetTxCIrq_sync2 <=#Tp 1'b0;  else    SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;endalways @ (posedge Clk or posedge Reset)begin  if(Reset)    SetTxCIrq_sync3 <=#Tp 1'b0;  else    SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2;endalways @ (posedge Clk or posedge Reset)begin  if(Reset)    SetTxCIrq <=#Tp 1'b0;  else    SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3;endalways @ (posedge TxClk or posedge Reset)begin  if(Reset)    ResetTxCIrq_sync1 <=#Tp 1'b0;  else    ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2;endalways @ (posedge TxClk or posedge Reset)begin  if(Reset)    ResetTxCIrq_sync2 <=#Tp 1'b0;  else    ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;end// Synchronizing RxC Interruptalways @ (posedge RxClk or posedge Reset)begin  if(Reset)    SetRxCIrq_rxclk <=#Tp 1'b0;  else  if(SetPauseTimer & r_RxFlow)    SetRxCIrq_rxclk <=#Tp 1'b1;  else  if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))    SetRxCIrq_rxclk <=#Tp 1'b0;endalways @ (posedge Clk or posedge Reset)begin  if(Reset)    SetRxCIrq_sync1 <=#Tp 1'b0;  else    SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk;endalways @ (posedge Clk or posedge Reset)begin  if(Reset)    SetRxCIrq_sync2 <=#Tp 1'b0;  else    SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;endalways @ (posedge Clk or posedge Reset)begin  if(Reset)    SetRxCIrq_sync3 <=#Tp 1'b0;  else    SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2;endalways @ (posedge Clk or posedge Reset)begin  if(Reset)    SetRxCIrq <=#Tp 1'b0;  else    SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3;endalways @ (posedge RxClk or posedge Reset)begin  if(Reset)    ResetRxCIrq_sync1 <=#Tp 1'b0;  else    ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;endalways @ (posedge RxClk or posedge Reset)begin  if(Reset)    ResetRxCIrq_sync2 <=#Tp 1'b0;  else    ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;endalways @ (posedge RxClk or posedge Reset)begin  if(Reset)    ResetRxCIrq_sync3 <=#Tp 1'b0;  else    ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;end// Interrupt generationalways @ (posedge Clk or posedge Reset)begin  if(Reset)    irq_txb <= 1'b0;  else  if(TxB_IRQ)    irq_txb <= #Tp 1'b1;  else  if(INT_SOURCE_Wr[0] & DataIn[0])    irq_txb <= #Tp 1'b0;endalways @ (posedge Clk or posedge Reset)begin  if(Reset)    irq_txe <= 1'b0;  else  if(TxE_IRQ)    irq_txe <= #Tp 1'b1;  else  if(INT_SOURCE_Wr[0] & DataIn[1])    irq_txe <= #Tp 1'b0;endalways @ (posedge Clk or posedge Reset)begin  if(Reset)    irq_rxb <= 1'b0;  else  if(RxB_IRQ)    irq_rxb <= #Tp 1'b1;  else  if(INT_SOURCE_Wr[0] & DataIn[2])    irq_rxb <= #Tp 1'b0;endalways @ (posedge Clk or posedge Reset)begin  if(Reset)    irq_rxe <= 1'b0;  else  if(RxE_IRQ)    irq_rxe <= #Tp 1'b1;  else  if(INT_SOURCE_Wr[0] & DataIn[3])    irq_rxe <= #Tp 1'b0;endalways @ (posedge Clk or posedge Reset)begin  if(Reset)    irq_busy <= 1'b0;  else  if(Busy_IRQ)    irq_busy <= #Tp 1'b1;  else  if(INT_SOURCE_Wr[0] & DataIn[4])    irq_busy <= #Tp 1'b0;endalways @ (posedge Clk or posedge Reset)begin  if(Reset)    irq_txc <= 1'b0;  else  if(SetTxCIrq)    irq_txc <= #Tp 1'b1;  else  if(INT_SOURCE_Wr[0] & DataIn[5])    irq_txc <= #Tp 1'b0;endalways @ (posedge Clk or posedge Reset)begin  if(Reset)    irq_rxc <= 1'b0;  else  if(SetRxCIrq)    irq_rxc <= #Tp 1'b1;  else  if(INT_SOURCE_Wr[0] & DataIn[6])    irq_rxc <= #Tp 1'b0;end// Generating interrupt signalassign int_o = irq_txb  & INT_MASKOut[0] |                irq_txe  & INT_MASKOut[1] |                irq_rxb  & INT_MASKOut[2] |                irq_rxe  & INT_MASKOut[3] |                irq_busy & INT_MASKOut[4] |                irq_txc  & INT_MASKOut[5] |                irq_rxc  & INT_MASKOut[6] ;// For reading interrupt statusassign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};endmodule