//////////////////////////////////////////////////////////////////////////                                                              ////////  eth_miim.v                                                  ////////                                                              ////////  This file is part of the Ethernet IP core project           ////////  http://www.opencores.org/projects/ethmac/                   ////////                                                              ////////  Author(s):                                                  ////////      - Igor Mohor (igorM@opencores.org)                      ////////                                                              ////////  All additional information is avaliable in the Readme.txt   ////////  file.                                                       ////////                                                              //////////////////////////////////////////////////////////////////////////////                                                              //////// Copyright (C) 2001 Authors                                   ////////                                                              //////// This source file may be used and distributed without         //////// restriction provided that this copyright statement is not    //////// removed from the file and that any derivative work contains  //////// the original copyright notice and the associated disclaimer. ////////                                                              //////// This source file is free software; you can redistribute it   //////// and/or modify it under the terms of the GNU Lesser General   //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any   //////// later version.                                               ////////                                                              //////// This source is distributed in the hope that it will be       //////// useful, but WITHOUT ANY WARRANTY; without even the implied   //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //////// PURPOSE.  See the GNU Lesser General Public License for more //////// details.                                                     ////////                                                              //////// You should have received a copy of the GNU Lesser General    //////// Public License along with this source; if not, download it   //////// from http://www.opencores.org/lgpl.shtml                     ////////                                                              ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: eth_miim.v,v $// Revision 1.7  2005/03/21 20:07:18  igorm// Some small fixes + some troubles fixed.//// Revision 1.6  2005/02/21 12:48:07  igorm// Warning fixes.//// Revision 1.5  2003/05/16 10:08:27  mohor// Busy was set 2 cycles too late. Reported by Dennis Scott.//// Revision 1.4  2002/08/14 18:32:10  mohor// - Busy signal was not set on time when scan status operation was performed// and clock was divided with more than 2.// - Nvalid remains valid two more clocks (was previously cleared too soon).//// Revision 1.3  2002/01/23 10:28:16  mohor// Link in the header changed.//// Revision 1.2  2001/10/19 08:43:51  mohor// eth_timescale.v changed to timescale.v This is done because of the// simulation of the few cores in a one joined project.//// Revision 1.1  2001/08/06 14:44:29  mohor// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).// Include files fixed to contain no path.// File names and module names changed ta have a eth_ prologue in the name.// File eth_timescale.v is used to define timescale// All pin names on the top module are changed to contain _I, _O or _OE at the end.// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O// and Mdo_OE. The bidirectional signal must be created on the top level. This// is done due to the ASIC tools.//// Revision 1.2  2001/08/02 09:25:31  mohor// Unconnected signals are now connected.//// Revision 1.1  2001/07/30 21:23:42  mohor// Directory structure changed. Files checked and joind together.//// Revision 1.3  2001/06/01 22:28:56  mohor// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.////`include "timescale.v"module eth_miim(  Clk,  Reset,  Divider,  NoPre,  CtrlData,  Rgad,  Fiad,  WCtrlData,  RStat,  ScanStat,  Mdi,  Mdo,  MdoEn,  Mdc,  Busy,  Prsd,  LinkFail,  Nvalid,  WCtrlDataStart,  RStatStart,  UpdateMIIRX_DATAReg);input         Clk;                // Host Clockinput         Reset;              // General Resetinput   [7:0] Divider;            // Divider for the host clockinput  [15:0] CtrlData;           // Control Data (to be written to the PHY reg.)input   [4:0] Rgad;               // Register Address (within the PHY)input   [4:0] Fiad;               // PHY Addressinput         NoPre;              // No Preamble (no 32-bit preamble)input         WCtrlData;          // Write Control Data operationinput         RStat;              // Read Status operationinput         ScanStat;           // Scan Status operationinput         Mdi;                // MII Management Data Inoutput        Mdc;                // MII Management Data Clockoutput        Mdo;                // MII Management Data Outputoutput        MdoEn;              // MII Management Data Output Enableoutput        Busy;               // Busy Signaloutput        LinkFail;           // Link Integrity Signaloutput        Nvalid;             // Invalid Status (qualifier for the valid scan result)output [15:0] Prsd;               // Read Status Data (data read from the PHY)output        WCtrlDataStart;     // This signals resets the WCTRLDATA bit in the MIIM Command registeroutput        RStatStart;         // This signal resets the RSTAT BIT in the MIIM Command registeroutput        UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read dataparameter Tp = 1;reg           Nvalid;reg           EndBusy_d;          // Pre-end Busy signalreg           EndBusy;            // End Busy signal (stops the operation in progress)reg           WCtrlData_q1;       // Write Control Data operation delayed 1 Clk cyclereg           WCtrlData_q2;       // Write Control Data operation delayed 2 Clk cyclesreg           WCtrlData_q3;       // Write Control Data operation delayed 3 Clk cyclesreg           WCtrlDataStart;     // Start Write Control Data Command (positive edge detected)reg           WCtrlDataStart_q;reg           WCtrlDataStart_q1;  // Start Write Control Data Command delayed 1 Mdc cyclereg           WCtrlDataStart_q2;  // Start Write Control Data Command delayed 2 Mdc cyclesreg           RStat_q1;           // Read Status operation delayed 1 Clk cyclereg           RStat_q2;           // Read Status operation delayed 2 Clk cyclesreg           RStat_q3;           // Read Status operation delayed 3 Clk cyclesreg           RStatStart;         // Start Read Status Command (positive edge detected)reg           RStatStart_q1;      // Start Read Status Command delayed 1 Mdc cyclereg           RStatStart_q2;      // Start Read Status Command delayed 2 Mdc cyclesreg           ScanStat_q1;        // Scan Status operation delayed 1 cyclereg           ScanStat_q2;        // Scan Status operation delayed 2 cyclesreg           SyncStatMdcEn;      // Scan Status operation delayed at least cycles and synchronized to MdcEnwire          WriteDataOp;        // Write Data Operation (positive edge detected)wire          ReadStatusOp;       // Read Status Operation (positive edge detected)wire          ScanStatusOp;       // Scan Status Operation (positive edge detected)wire          StartOp;            // Start Operation (start of any of the preceding operations)wire          EndOp;              // End of Operationreg           InProgress;         // Operation in progressreg           InProgress_q1;      // Operation in progress delayed 1 Mdc cyclereg           InProgress_q2;      // Operation in progress delayed 2 Mdc cyclesreg           InProgress_q3;      // Operation in progress delayed 3 Mdc cyclesreg           WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)reg     [6:0] BitCounter;         // Bit Counterwire    [3:0] ByteSelect;         // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.wire          MdcEn;              // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.wire          ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signalwire          MdcEn_n;wire          LatchByte1_d2;wire          LatchByte0_d2;reg           LatchByte1_d;reg           LatchByte0_d;reg     [1:0] LatchByte;          // Latch Byte selects which part of Read Status Data is updated from the shift registerreg           UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data// Generation of the EndBusy signal. It is used for ending the MII Management operation.always @ (posedge Clk or posedge Reset)begin  if(Reset)    begin      EndBusy_d <= #Tp 1'b0;      EndBusy <= #Tp 1'b0;    end  else    begin      EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3;      EndBusy   <= #Tp EndBusy_d;    endend// Update MII RX_DATA registeralways @ (posedge Clk or posedge Reset)begin  if(Reset)    UpdateMIIRX_DATAReg <= #Tp 0;  else  if(EndBusy & ~WCtrlDataStart_q)    UpdateMIIRX_DATAReg <= #Tp 1;  else    UpdateMIIRX_DATAReg <= #Tp 0;    end