?? mem_interface_top_ddr_controller_0.txt
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2005 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : $Name: mig_v1_7 $
// \ \ Application : MIG
// / / Filename : mem_interface_top_ddr_controller_0.v
// /___/ /\ Date Last Modified : $Date: 2007/02/16 12:58:56 $
// \ \ / \ Date Created : Mon May 2 2005
// \___\/\___\
//
// Device : Virtex-4
// Design Name : DDR SDRAM
// Description: This is the main control logic of the memory interface. All
// commands are issued from here acoording to the burst,
// CAS Latency and the user commands.
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`include "../rtl/mem_interface_top_parameters_0.v"
module mem_interface_top_ddr_controller_0
(
input clk_0,
input rst,
input [35:0] af_addr,
input af_empty,
input comp_done,
input phy_Dly_Slct_Done,
output reg ctrl_Dummyread_Start,
output ctrl_af_RdEn,
output ctrl_Wdf_RdEn,
output ctrl_Dqs_Rst,
output ctrl_Dqs_En,
output ctrl_WrEn,
output ctrl_RdEn,
output[`row_address-1:0] ctrl_ddr_address,
output[`bank_address-1:0] ctrl_ddr_ba,
output ctrl_ddr_ras_L,
output ctrl_ddr_cas_L,
output ctrl_ddr_we_L,
output [`no_of_cs-1:0] ctrl_ddr_cs_L,
output [`cke_width-1:0] ctrl_ddr_cke,
output reg init_done,
output [2:0] burst_length,
output dummy_write_pattern
);
reg [3:0] init_count;
reg [3:0] init_count_cp;
reg init_memory;
reg [7:0] count_200_cycle;
reg ref_flag_0;
reg ref_flag_0_r;
reg auto_ref;
reg [5:0] next_state;
reg [5:0] state;
reg [5:0] state_r2;
reg [5:0] state_r3;
reg [5:0] init_next_state;
reg [5:0] init_state;
reg [5:0] init_state_r2;
reg [5:0] init_state_r3;
reg [`row_address -1:0] row_addr_r;
reg [`row_address -1:0] ddr_address_init_r;
reg [`row_address -1:0] ddr_address_r1;
reg [`bank_address-1:0] ddr_ba_r1;
// counters for ddr controller
reg mrd_count;
reg [2:0] rp_count;
reg [5:0] rfc_count;
reg [2:0] rcd_count;
reg [3:0] ras_count;
reg [3:0] wr_to_rd_count;
reg [3:0] rd_to_wr_count;
reg [3:0] rtp_count;
reg [3:0] wtp_count;
reg [`max_ref_width - 1:0] refi_count;
reg [2:0] cas_count;
reg [3:0] cas_check_count;
reg [2:0] wrburst_cnt;
reg [2:0] read_burst_cnt;
reg [2:0] ctrl_WrEn_cnt;
reg [2:0] rdburst_cnt;
reg [35:0] af_addr_r;
reg wdf_rden_r;
reg wdf_rden_r2;
reg wdf_rden_r3;
reg wdf_rden_r4;
reg ddr_ras_r2;
reg ddr_cas_r2;
reg ddr_we_r2;
reg ddr_ras_r;
reg ddr_cas_r;
reg ddr_we_r;
reg ddr_ras_r3;
reg ddr_cas_r3;
reg ddr_we_r3;
reg [3:0] idle_cnt;
reg ctrl_Dummyread_Start_r1;
reg ctrl_Dummyread_Start_r2;
reg ctrl_Dummyread_Start_r3;
reg ctrl_Dummyread_Start_r4;
reg conflict_resolved_r;
reg rst_r;
reg [`no_of_cs-1:0] ddr_cs_r1;
reg [`no_of_cs-1:0] ddr_cs_r;
reg [`cke_width-1:0] ddr_cke_r;
reg [1:0] chip_cnt;
reg dummy_read_en;
reg count_200cycle_done_r;
reg init_done_int;
reg conflict_detect_r;
reg [14:0] load_mode_reg;
reg [14:0] ext_mode_reg;
reg WR;
reg RD;
reg LMR;
reg PRE;
reg REF;
reg ACT;
reg WR_r;
reg RD_r;
reg LMR_r;
reg PRE_r;
reg REF_r;
reg ACT_r;
reg af_empty_r;
reg LMR_PRE_REF_ACT_cmd_r;
reg [4:0] cke_200us_cnt;
reg done_200us;
reg burst_read_state_r2;
reg burst_read_state_r3;
reg first_read_state_r2;
reg read_write_state_r2;
reg ctrl_Wdf_RdEn_r; // added for dimm
reg ctrl_Wdf_RdEn_r1;
reg ctrl_Dqs_Rst_r;
reg ctrl_Dqs_Rst_r1;
reg ctrl_WrEn_r;
reg ctrl_WrEn_r1;
reg ctrl_RdEn_r;
reg ctrl_RdEn_r1;
reg ctrl_Dqs_En_r;
reg ctrl_Dqs_En_r1;
reg dummy_write_state_r;
reg pattern_read_state_r2;
reg pattern_read_state_r3;
reg pattern_read_state_1_r2;
reg dummy_write_flag;
reg dummy_write_pattern_2;
reg [`row_address-1 : 0] ddr_address_r2;
reg [`bank_address-1 : 0] ddr_ba_r2;
reg [4:0] count5;
wire ctrl_init_done;
wire [`row_address -1:0] ddr_address_BL;
wire [2:0] burst_cnt;
wire ref_flag;
wire conflict_detect;
wire [2:0] CAS_LATENCY_VALUE;
wire [2:0] BURST_LENGTH_VALUE;
wire registered_dimm;
wire [2:0] command_address;
wire write_state;
wire read_state;
wire read_write_state;
wire burst_write_state;
wire first_write_state;
wire burst_read_state;
wire first_read_state;
wire af_rden;
wire dummy_write_state;
wire dummy_write_state_1;
wire pattern_read_state;
wire pattern_read_state_1;
wire dummy_write_pattern_1;
localparam cntnext = 5'b11000;
localparam IDLE = 5'h00;
localparam LOAD_MODE_REG_ST = 5'h01;
localparam MODE_REGISTER_WAIT = 5'h02;
localparam PRECHARGE = 5'h03;
localparam PRECHARGE_WAIT = 5'h04;
localparam AUTO_REFRESH = 5'h05;
localparam AUTO_REFRESH_WAIT = 5'h06;
localparam ACTIVE = 5'h07;
localparam ACTIVE_WAIT = 5'h08;
localparam FIRST_WRITE = 5'h09;
localparam BURST_WRITE = 5'h0A;
localparam WRITE_WAIT = 5'h0B;
localparam WRITE_READ = 5'h0C;
localparam FIRST_READ = 5'h0D;
localparam BURST_READ = 5'h0E;
localparam READ_WAIT = 5'h0F;
localparam READ_WRITE = 5'h10;
localparam INIT_IDLE = 5'h01;
localparam INIT_DEEP_MEMORY_ST = 5'h02;
localparam INIT_INITCOUNT_200 = 5'h03;
localparam INIT_INITCOUNT_200_WAIT = 5'h04;
localparam INIT_DUMMY_READ_CYCLES = 5'h05;
localparam INIT_DUMMY_ACTIVE = 5'h06;
localparam INIT_DUMMY_ACTIVE_WAIT = 5'h07;
localparam INIT_DUMMY_FIRST_READ = 5'h08;
localparam INIT_DUMMY_READ = 5'h09;
localparam INIT_DUMMY_READ_WAIT = 5'h0A;
localparam INIT_DUMMY_WRITE1 = 5'h0B;
localparam INIT_DUMMY_WRITE2 = 5'h0C;
localparam INIT_DUMMY_WRITE_READ = 5'h0D;
localparam INIT_PATTERN_READ1 = 5'h0E;
localparam INIT_PATTERN_READ2 = 5'h0F;
localparam INIT_PATTERN_READ_WAIT = 5'h10;
localparam INIT_PRECHARGE = 5'h11;
localparam INIT_PRECHARGE_WAIT = 5'h12;
localparam INIT_AUTO_REFRESH = 5'h13;
localparam INIT_AUTO_REFRESH_WAIT = 5'h14;
localparam INIT_LOAD_MODE_REG_ST = 5'h15;
localparam INIT_MODE_REGISTER_WAIT = 5'h16;
assign registered_dimm = `registered;
assign CAS_LATENCY_VALUE = (load_mode_reg[6:4]==3'b110)?3'b010:load_mode_reg[6:4] ;
assign BURST_LENGTH_VALUE = load_mode_reg[2:0];
assign burst_length = burst_cnt;
assign command_address = af_addr[34:32];
assign burst_read_state = ~((conflict_detect & (~conflict_resolved_r))) &
((state == BURST_READ)) & RD;
assign first_read_state = ~((conflict_detect & (~conflict_resolved_r))) &
((state == FIRST_READ) ) & RD;
assign read_state = burst_read_state || first_read_state;
assign read_write_state = write_state || read_state;
assign burst_write_state = ~((conflict_detect & (~conflict_resolved_r))) &
((state == BURST_WRITE)) & WR;
assign first_write_state = ~((conflict_detect & (~conflict_resolved_r))) &
((state == FIRST_WRITE) ) & WR;
assign write_state = burst_write_state || first_write_state;
assign dummy_write_state = ((init_state == INIT_DUMMY_WRITE1)
|| (init_state == INIT_DUMMY_WRITE2));
assign dummy_write_state_1 = (init_state == INIT_DUMMY_WRITE1);
assign dummy_write_pattern_1 = ((init_state == INIT_DUMMY_WRITE1)
|| (init_state == INIT_DUMMY_WRITE2) ||
(init_state == INIT_DUMMY_WRITE_READ));
assign pattern_read_state = ((init_state == INIT_PATTERN_READ1)
|| (init_state == INIT_PATTERN_READ2));
assign pattern_read_state_1 = (init_state == INIT_PATTERN_READ1);
always @( posedge clk_0 )
rst_r <= rst;
always @(posedge clk_0) begin
if(rst_r)
dummy_write_pattern_2 <= 1'b0;
else
dummy_write_pattern_2 <= dummy_write_pattern_1;
end
assign dummy_write_pattern = (registered_dimm) ? dummy_write_pattern_2
: dummy_write_pattern_1;
// fifo control signals
assign ctrl_af_RdEn = af_rden;
assign conflict_detect = af_addr[35]& ctrl_init_done & ~af_empty;
always @ (posedge clk_0) begin
if(rst_r) begin
pattern_read_state_r2 <= 1'b0;
pattern_read_state_r3 <= 1'b0;
end
else begin
pattern_read_state_r2 <= pattern_read_state;
pattern_read_state_r3 <= pattern_read_state_r2;
end
end
always @ (posedge clk_0) begin
if(rst_r)
pattern_read_state_1_r2 <= 1'b0;
else
pattern_read_state_1_r2 <= pattern_read_state_1;
end
always @ (posedge clk_0) begin
if(rst_r)
dummy_write_state_r <= 1'b0;
else
dummy_write_state_r <= dummy_write_state;
end
//commands
always @(command_address or ctrl_init_done or af_empty) begin
WR = 1'b0;
RD = 1'b0;
LMR = 1'b0;
PRE = 1'b0;
REF = 1'b0;
ACT = 1'b0;
if(ctrl_init_done & ~af_empty) begin
case(command_address)
3'b000: LMR = 1'b1;
3'b001: REF = 1'b1;
3'b010: PRE = 1'b1;
3'b011: ACT = 1'b1;
3'b100: WR = 1'b1;
3'b101: RD = 1'b1;
endcase
end
end
// register address outputs
always @ (posedge clk_0) begin
if (rst_r) begin
WR_r <= 1'b0;
RD_r <= 1'b0;
LMR_r <= 1'b0;
PRE_r <= 1'b0;
REF_r <= 1'b0;
ACT_r <= 1'b0;
af_empty_r <= 1'b0;
LMR_PRE_REF_ACT_cmd_r <= 1'b0;
end
else begin
WR_r <= WR;
RD_r <= RD;
LMR_r <= LMR;
PRE_r <= PRE;
REF_r <= REF;
ACT_r <= ACT;
LMR_PRE_REF_ACT_cmd_r <= LMR | PRE | REF | ACT;
af_empty_r <= af_empty;
end // else: !if(rst_r)
end // always @ (posedge clk_0)
// register address outputs
always @ (posedge clk_0) begin
if (rst_r) begin
af_addr_r <= 36'h00000;
conflict_detect_r <= 1'b0;
read_write_state_r2 <= 1'b0;
first_read_state_r2 <= 1'b0;
burst_read_state_r2 <= 1'b0;
burst_read_state_r3 <= 1'b0;
end
else begin
af_addr_r <= af_addr;
conflict_detect_r <= conflict_detect;
read_write_state_r2 <= read_write_state;
first_read_state_r2 <= first_read_state;
burst_read_state_r2 <= burst_read_state;
burst_read_state_r3 <= burst_read_state_r2;
end
end
always @ (posedge clk_0) begin
if (rst_r) begin
load_mode_reg <= `load_mode_register;
end
else if(((state==LOAD_MODE_REG_ST) || (init_state==INIT_LOAD_MODE_REG_ST))
& LMR_r &(af_addr_r[(`bank_address+`row_address + `col_ap_width)-1:
(`col_ap_width + `row_address)]==2'b00))
load_mode_reg <= af_addr [`row_address-1:0];
end
always @ (posedge clk_0) begin
if (rst_r) begin
ext_mode_reg <= `ext_load_mode_register;
end
else if(((state==LOAD_MODE_REG_ST) || (init_state==INIT_LOAD_MODE_REG_ST))
& LMR_r &(af_addr_r[(`bank_address+`row_address + `col_ap_width)-1:
(`col_ap_width + `row_address)]==2'b01) )
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