{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Aug 11 17:52:57 2006 " "Info: Processing started: Fri Aug 11 17:52:57 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off freedev_cycloneII_50 -c freedev_cycloneII_50 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off freedev_cycloneII_50 -c freedev_cycloneII_50" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "freedev_cycloneII_50_top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file freedev_cycloneII_50_top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 freedev_cycloneII_50_top " "Info: Found entity 1: freedev_cycloneII_50_top" {  } { { "freedev_cycloneII_50_top.bdf" "" { Schematic "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50_top.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "freedev_cycloneII_50_top " "Info: Elaborating entity \"freedev_cycloneII_50_top\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "freedev_cycloneII_50.v 15 15 " "Info: Using design file freedev_cycloneII_50.v, which is not specified as a design file for the current project, but contains definitions for 15 design units and 15 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 asmi_asmi_control_port_arbitrator " "Info: Found entity 1: asmi_asmi_control_port_arbitrator" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 21 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 cpu_0_data_master_arbitrator " "Info: Found entity 2: cpu_0_data_master_arbitrator" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 270 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 cpu_0_instruction_master_arbitrator " "Info: Found entity 3: cpu_0_instruction_master_arbitrator" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 626 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "4 data_RAM_s1_arbitrator " "Info: Found entity 4: data_RAM_s1_arbitrator" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 870 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "5 firmware_ROM_s1_arbitrator " "Info: Found entity 5: firmware_ROM_s1_arbitrator" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1269 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "6 jtag_uart_0_avalon_jtag_slave_arbitrator " "Info: Found entity 6: jtag_uart_0_avalon_jtag_slave_arbitrator" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1668 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "7 payload_buffer_s1_arbitrator " "Info: Found entity 7: payload_buffer_s1_arbitrator" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1919 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "8 sysid_control_slave_arbitrator " "Info: Found entity 8: sysid_control_slave_arbitrator" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 2340 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "9 tri_state_bridge_0_avalon_slave_arbitrator " "Info: Found entity 9: tri_state_bridge_0_avalon_slave_arbitrator" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 2527 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "10 tri_state_bridge_0_bridge_arbitrator " "Info: Found entity 10: tri_state_bridge_0_bridge_arbitrator" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 3175 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "11 freedev_cycloneII_50_reset_clk_domain_synch_module " "Info: Found entity 11: freedev_cycloneII_50_reset_clk_domain_synch_module" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 3183 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "12 freedev_cycloneII_50 " "Info: Found entity 12: freedev_cycloneII_50" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 3223 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "13 cfi_flash_0_lane0_module " "Info: Found entity 13: cfi_flash_0_lane0_module" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 3830 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "14 cfi_flash_0_lane1_module " "Info: Found entity 14: cfi_flash_0_lane1_module" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 3916 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "15 cfi_flash_0 " "Info: Found entity 15: cfi_flash_0" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 4002 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "freedev_cycloneII_50 freedev_cycloneII_50:inst " "Info: Elaborating entity \"freedev_cycloneII_50\" for hierarchy \"freedev_cycloneII_50:inst\"" {  } { { "freedev_cycloneII_50_top.bdf" "inst" { Schematic "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50_top.bdf" { { 40 632 896 216 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(3819) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(3819): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 3819 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(3823) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(3823): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 3823 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asmi_asmi_control_port_arbitrator freedev_cycloneII_50:inst\|asmi_asmi_control_port_arbitrator:the_asmi_asmi_control_port " "Info: Elaborating entity \"asmi_asmi_control_port_arbitrator\" for hierarchy \"freedev_cycloneII_50:inst\|asmi_asmi_control_port_arbitrator:the_asmi_asmi_control_port\"" {  } { { "freedev_cycloneII_50.v" "the_asmi_asmi_control_port" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 3420 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(127) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(127): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 127 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "freedev_cycloneII_50.v(128) " "Warning: (10037) Verilog HDL or VHDL warning at freedev_cycloneII_50.v(128): condition expression evaluates to a constant" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 128 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 freedev_cycloneII_50.v(145) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(145): truncated value with size 32 to match size of target (2)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 145 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 freedev_cycloneII_50.v(148) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(148): truncated value with size 32 to match size of target (2)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 148 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 freedev_cycloneII_50.v(163) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(163): truncated value with size 32 to match size of target (2)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 163 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(173) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(173): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 173 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(183) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(183): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 183 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(186) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(186): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 186 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 freedev_cycloneII_50.v(190) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(190): truncated value with size 32 to match size of target (16)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 190 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(202) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(202): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 202 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(205) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(205): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 205 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(208) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(208): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 208 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "28 3 freedev_cycloneII_50.v(230) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(230): truncated value with size 28 to match size of target (3)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 230 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(236) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(236): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 236 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "freedev_cycloneII_50.v(237) " "Warning: (10037) Verilog HDL or VHDL warning at freedev_cycloneII_50.v(237): condition expression evaluates to a constant" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 237 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(260) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(260): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 260 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "cpu_0_data_master_read_data_valid_asmi_asmi_control_port freedev_cycloneII_50.v(67) " "Warning: Output port \"cpu_0_data_master_read_data_valid_asmi_asmi_control_port\" at freedev_cycloneII_50.v(67) has no driver" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 67 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "asmi.v 3 3 " "Info: Using design file asmi.v, which is not specified as a design file for the current project, but contains definitions for 3 design units and 3 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 asmi_sub " "Info: Found entity 1: asmi_sub" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 36 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 tornado_asmi_atom " "Info: Found entity 2: tornado_asmi_atom" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 418 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 asmi " "Info: Found entity 3: asmi" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 461 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asmi freedev_cycloneII_50:inst\|asmi:the_asmi " "Info: Elaborating entity \"asmi\" for hierarchy \"freedev_cycloneII_50:inst\|asmi:the_asmi\"" {  } { { "freedev_cycloneII_50.v" "the_asmi" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 3436 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "asmi_sub freedev_cycloneII_50:inst\|asmi:the_asmi\|asmi_sub:the_asmi_sub " "Info: Elaborating entity \"asmi_sub\" for hierarchy \"freedev_cycloneII_50:inst\|asmi:the_asmi\|asmi_sub:the_asmi_sub\"" {  } { { "asmi.v" "the_asmi_sub" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 519 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(138) " "Warning: Verilog HDL assignment warning at asmi.v(138): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 138 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "asmi.v(139) " "Warning: (10037) Verilog HDL or VHDL warning at asmi.v(139): condition expression evaluates to a constant" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(148) " "Warning: Verilog HDL assignment warning at asmi.v(148): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 148 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "asmi.v(149) " "Warning: (10037) Verilog HDL or VHDL warning at asmi.v(149): condition expression evaluates to a constant" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 149 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(159) " "Warning: Verilog HDL assignment warning at asmi.v(159): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 159 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "asmi.v(160) " "Warning: (10037) Verilog HDL or VHDL warning at asmi.v(160): condition expression evaluates to a constant" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 160 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 asmi.v(169) " "Warning: Verilog HDL assignment warning at asmi.v(169): truncated value with size 32 to match size of target (1)" {  } { { "asmi.v" "" { Text "J:/board/freedev_cycloneII_50/system/asmi.v" 169 0 0 } }  } 0}