{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 freedev_cycloneII_50.v(771) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(771): truncated value with size 32 to match size of target (16)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 771 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 freedev_cycloneII_50.v(778) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(778): truncated value with size 32 to match size of target (2)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 778 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 freedev_cycloneII_50.v(795) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(795): truncated value with size 32 to match size of target (2)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 795 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "cpu_0.v 2 2 " "Info: Using design file cpu_0.v, which is not specified as a design file for the current project, but contains definitions for 2 design units and 2 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_rf_module " "Info: Found entity 1: cpu_0_rf_module" {  } { { "cpu_0.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0.v" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 cpu_0 " "Info: Found entity 2: cpu_0" {  } { { "cpu_0.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0.v" 97 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0 freedev_cycloneII_50:inst\|cpu_0:the_cpu_0 " "Info: Elaborating entity \"cpu_0\" for hierarchy \"freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\"" {  } { { "freedev_cycloneII_50.v" "the_cpu_0" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 3563 -1 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "cpu_0_test_bench.v 1 1 " "Info: Using design file cpu_0_test_bench.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_test_bench " "Info: Found entity 1: cpu_0_test_bench" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_test_bench freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|cpu_0_test_bench:the_cpu_0_test_bench " "Info: Elaborating entity \"cpu_0_test_bench\" for hierarchy \"freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|cpu_0_test_bench:the_cpu_0_test_bench\"" {  } { { "cpu_0.v" "the_cpu_0_test_bench" { Text "J:/board/freedev_cycloneII_50/system/cpu_0.v" 681 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "D_inst cpu_0_test_bench.v(80) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(80): object \"D_inst\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 80 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "W_vinst cpu_0_test_bench.v(209) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(209): object \"W_vinst\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 209 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_0_is_x cpu_0_test_bench.v(211) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(211): object \"av_ld_data_aligned_unfiltered_0_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 211 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_10_is_x cpu_0_test_bench.v(212) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(212): object \"av_ld_data_aligned_unfiltered_10_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 212 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_11_is_x cpu_0_test_bench.v(213) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(213): object \"av_ld_data_aligned_unfiltered_11_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 213 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_12_is_x cpu_0_test_bench.v(214) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(214): object \"av_ld_data_aligned_unfiltered_12_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 214 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_13_is_x cpu_0_test_bench.v(215) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(215): object \"av_ld_data_aligned_unfiltered_13_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 215 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_14_is_x cpu_0_test_bench.v(216) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(216): object \"av_ld_data_aligned_unfiltered_14_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 216 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_15_is_x cpu_0_test_bench.v(217) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(217): object \"av_ld_data_aligned_unfiltered_15_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 217 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_16_is_x cpu_0_test_bench.v(218) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(218): object \"av_ld_data_aligned_unfiltered_16_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 218 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_17_is_x cpu_0_test_bench.v(219) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(219): object \"av_ld_data_aligned_unfiltered_17_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 219 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_18_is_x cpu_0_test_bench.v(220) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(220): object \"av_ld_data_aligned_unfiltered_18_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 220 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_19_is_x cpu_0_test_bench.v(221) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(221): object \"av_ld_data_aligned_unfiltered_19_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 221 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_1_is_x cpu_0_test_bench.v(222) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(222): object \"av_ld_data_aligned_unfiltered_1_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 222 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_20_is_x cpu_0_test_bench.v(223) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(223): object \"av_ld_data_aligned_unfiltered_20_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 223 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_21_is_x cpu_0_test_bench.v(224) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(224): object \"av_ld_data_aligned_unfiltered_21_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 224 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_22_is_x cpu_0_test_bench.v(225) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(225): object \"av_ld_data_aligned_unfiltered_22_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 225 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_23_is_x cpu_0_test_bench.v(226) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(226): object \"av_ld_data_aligned_unfiltered_23_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 226 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_24_is_x cpu_0_test_bench.v(227) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(227): object \"av_ld_data_aligned_unfiltered_24_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 227 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_25_is_x cpu_0_test_bench.v(228) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(228): object \"av_ld_data_aligned_unfiltered_25_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 228 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_26_is_x cpu_0_test_bench.v(229) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(229): object \"av_ld_data_aligned_unfiltered_26_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 229 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_27_is_x cpu_0_test_bench.v(230) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(230): object \"av_ld_data_aligned_unfiltered_27_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 230 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_28_is_x cpu_0_test_bench.v(231) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(231): object \"av_ld_data_aligned_unfiltered_28_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 231 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_29_is_x cpu_0_test_bench.v(232) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(232): object \"av_ld_data_aligned_unfiltered_29_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 232 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_2_is_x cpu_0_test_bench.v(233) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(233): object \"av_ld_data_aligned_unfiltered_2_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 233 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_30_is_x cpu_0_test_bench.v(234) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(234): object \"av_ld_data_aligned_unfiltered_30_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 234 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_31_is_x cpu_0_test_bench.v(235) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(235): object \"av_ld_data_aligned_unfiltered_31_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 235 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_3_is_x cpu_0_test_bench.v(236) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(236): object \"av_ld_data_aligned_unfiltered_3_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 236 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_4_is_x cpu_0_test_bench.v(237) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(237): object \"av_ld_data_aligned_unfiltered_4_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 237 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_5_is_x cpu_0_test_bench.v(238) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(238): object \"av_ld_data_aligned_unfiltered_5_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 238 0 0 } }  } 0}