{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_6_is_x cpu_0_test_bench.v(239) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(239): object \"av_ld_data_aligned_unfiltered_6_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 239 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_7_is_x cpu_0_test_bench.v(240) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(240): object \"av_ld_data_aligned_unfiltered_7_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 240 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_8_is_x cpu_0_test_bench.v(241) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(241): object \"av_ld_data_aligned_unfiltered_8_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 241 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_9_is_x cpu_0_test_bench.v(242) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(242): object \"av_ld_data_aligned_unfiltered_9_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 242 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 cpu_0_test_bench.v(249) " "Warning: Verilog HDL assignment warning at cpu_0_test_bench.v(249): truncated value with size 32 to match size of target (1)" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 249 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "cpu_0_test_bench.v(250) " "Warning: (10037) Verilog HDL or VHDL warning at cpu_0_test_bench.v(250): condition expression evaluates to a constant" {  } { { "cpu_0_test_bench.v" "" { Text "J:/board/freedev_cycloneII_50/system/cpu_0_test_bench.v" 250 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_rf_module freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf " "Info: Elaborating entity \"cpu_0_rf_module\" for hierarchy \"freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf\"" {  } { { "cpu_0.v" "cpu_0_rf" { Text "J:/board/freedev_cycloneII_50/system/cpu_0.v" 1136 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "the_altsyncram" { Text "J:/board/freedev_cycloneII_50/system/cpu_0.v" 66 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_vuo1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_vuo1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_vuo1 " "Info: Found entity 1: altsyncram_vuo1" {  } { { "db/altsyncram_vuo1.tdf" "" { Text "J:/board/freedev_cycloneII_50/system/db/altsyncram_vuo1.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_vuo1 freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf\|altsyncram:the_altsyncram\|altsyncram_vuo1:auto_generated " "Info: Elaborating entity \"altsyncram_vuo1\" for hierarchy \"freedev_cycloneII_50:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf\|altsyncram:the_altsyncram\|altsyncram_vuo1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_RAM_s1_arbitrator freedev_cycloneII_50:inst\|data_RAM_s1_arbitrator:the_data_RAM_s1 " "Info: Elaborating entity \"data_RAM_s1_arbitrator\" for hierarchy \"freedev_cycloneII_50:inst\|data_RAM_s1_arbitrator:the_data_RAM_s1\"" {  } { { "freedev_cycloneII_50.v" "the_data_RAM_s1" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 3595 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(995) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(995): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 995 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "freedev_cycloneII_50.v(996) " "Warning: (10037) Verilog HDL or VHDL warning at freedev_cycloneII_50.v(996): condition expression evaluates to a constant" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 996 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 freedev_cycloneII_50.v(1010) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1010): truncated value with size 32 to match size of target (2)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1010 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 freedev_cycloneII_50.v(1013) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1013): truncated value with size 32 to match size of target (2)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1013 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 freedev_cycloneII_50.v(1031) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1031): truncated value with size 32 to match size of target (2)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1031 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(1041) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1041): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1041 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(1057) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1057): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1057 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "freedev_cycloneII_50.v(1058) " "Warning: (10037) Verilog HDL or VHDL warning at freedev_cycloneII_50.v(1058): condition expression evaluates to a constant" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1058 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(1059) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1059): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1059 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 freedev_cycloneII_50.v(1075) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1075): truncated value with size 2 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1075 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(1081) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1081): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1081 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "freedev_cycloneII_50.v(1082) " "Warning: (10037) Verilog HDL or VHDL warning at freedev_cycloneII_50.v(1082): condition expression evaluates to a constant" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1082 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(1101) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1101): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1101 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "freedev_cycloneII_50.v(1102) " "Warning: (10037) Verilog HDL or VHDL warning at freedev_cycloneII_50.v(1102): condition expression evaluates to a constant" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1102 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(1103) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1103): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1103 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 freedev_cycloneII_50.v(1115) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1115): truncated value with size 2 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1115 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(1121) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1121): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1121 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "freedev_cycloneII_50.v(1122) " "Warning: (10037) Verilog HDL or VHDL warning at freedev_cycloneII_50.v(1122): condition expression evaluates to a constant" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1122 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 freedev_cycloneII_50.v(1161) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1161): truncated value with size 32 to match size of target (2)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1161 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 freedev_cycloneII_50.v(1172) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1172): truncated value with size 32 to match size of target (2)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1172 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 freedev_cycloneII_50.v(1178) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1178): truncated value with size 32 to match size of target (2)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1178 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "28 8 freedev_cycloneII_50.v(1198) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1198): truncated value with size 28 to match size of target (8)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1198 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 freedev_cycloneII_50.v(1205) " "Warning: Verilog HDL assignment warning at freedev_cycloneII_50.v(1205): truncated value with size 32 to match size of target (1)" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_cycloneII_50/system/freedev_cycloneII_50.v" 1205 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "freedev_cycloneII_50.v(1206) " "Warning: (10037) Verilog HDL or VHDL warning at freedev_cycloneII_50.v(1206): condition expression evaluates to a constant" {  } { { "freedev_cycloneII_50.v" "" { Text "J:/board/freedev_c