?? adcint.vhd
字號:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADCINT IS
PORT(D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --來自0809轉(zhuǎn)換好的8位數(shù)據(jù)
CLK : IN STD_LOGIC; --狀態(tài)機(jī)工作時鐘
EOC : IN STD_LOGIC; --轉(zhuǎn)換狀態(tài)指示,低電平表示正在轉(zhuǎn)換
ALE : OUT STD_LOGIC; --8個模擬信號通道地址鎖存信號
START : OUT STD_LOGIC; --轉(zhuǎn)換開始信號
OE : OUT STD_LOGIC; --數(shù)據(jù)輸出3態(tài)控制信號
ADDA : OUT STD_LOGIC; --信號通道最低位控制信號
LOCK0 : OUT STD_LOGIC; --觀察數(shù)據(jù)鎖存時鐘
Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --8位數(shù)據(jù)輸出
END ADCINT;
ARCHITECTURE behav OF ADCINT IS
TYPE states IS (st0, st1, st2, st3,st4) ; --定義各狀態(tài)子類型
SIGNAL current_state, next_state: states :=st0 ;
SIGNAL REGL : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LOCK : STD_LOGIC; -- 轉(zhuǎn)換后數(shù)據(jù)輸出鎖存時鐘信號
BEGIN
ADDA <= '1';--當(dāng)ADDA<='0',模擬信號進(jìn)入通道IN0;當(dāng)ADDA<='1',則進(jìn)入通道IN1
Q <= REGL; LOCK0 <= LOCK ;
COM: PROCESS(current_state,EOC) BEGIN --規(guī)定各狀態(tài)轉(zhuǎn)換方式
CASE current_state IS
WHEN st0=>ALE<='0';START<='0';LOCK<='0';OE<='0';
next_state <= st1; --0809初始化
WHEN st1=>ALE<='1';START<='1';LOCK<='0';OE<='0';
next_state <= st2; --啟動采樣
WHEN st2=> ALE<='0';START<='0';LOCK<='0';OE<='0';
IF (EOC='1') THEN next_state <= st3; --EOC=1表明轉(zhuǎn)換結(jié)束
ELSE next_state <= st2; END IF ; --轉(zhuǎn)換未結(jié)束,繼續(xù)等待
WHEN st3=> ALE<='0';START<='0';LOCK<='0';OE<='1';
next_state <= st4;--開啟OE,輸出轉(zhuǎn)換好的數(shù)據(jù)
WHEN st4=> ALE<='0';START<='0';LOCK<='1';OE<='1'; next_state <= st0;
WHEN OTHERS => next_state <= st0;
END CASE ;
END PROCESS COM ;
REG: PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK='1') THEN current_state<=next_state; END IF;
END PROCESS REG ; -- 由信號current_state將當(dāng)前狀態(tài)值帶出此進(jìn)程:REG
LATCH1: PROCESS (LOCK) -- 此進(jìn)程中,在LOCK的上升沿,將轉(zhuǎn)換好的數(shù)據(jù)鎖入
BEGIN
IF LOCK='1' AND LOCK'EVENT THEN REGL <= D ; END IF;
END PROCESS LATCH1 ;
END behav;
?? 快捷鍵說明
復(fù)制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -