Timing Analyzer report for ADCINT
Mon Dec 18 21:22:13 2006
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'CLK'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                              ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From              ; To                ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 4.838 ns                                       ; EOC               ; current_state.st3 ; --         ; CLK      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 11.248 ns                                      ; REGL[0]           ; Q[0]              ; CLK        ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; 1.047 ns                                       ; D[1]              ; REGL[1]           ; --         ; CLK      ; 0            ;
; Clock Setup: 'CLK'           ; N/A   ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st2 ; current_state.st3 ; CLK        ; CLK      ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                   ;                   ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                         ;
+-------+------------------------------------------------+-------------------+-------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From              ; To                ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------------+-------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st2 ; current_state.st2 ; CLK        ; CLK      ; None                        ; None                      ; 1.040 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st2 ; current_state.st3 ; CLK        ; CLK      ; None                        ; None                      ; 1.040 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st4 ; current_state.st0 ; CLK        ; CLK      ; None                        ; None                      ; 1.017 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st1 ; current_state.st2 ; CLK        ; CLK      ; None                        ; None                      ; 0.825 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st0 ; current_state.st1 ; CLK        ; CLK      ; None                        ; None                      ; 0.822 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; current_state.st3 ; current_state.st4 ; CLK        ; CLK      ; None                        ; None                      ; 0.637 ns                ;
+-------+------------------------------------------------+-------------------+-------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------+
; tsu                                                                     ;
+-------+--------------+------------+------+-------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To                ; To Clock ;
+-------+--------------+------------+------+-------------------+----------+
; N/A   ; None         ; 4.838 ns   ; EOC  ; current_state.st3 ; CLK      ;
; N/A   ; None         ; 4.837 ns   ; EOC  ; current_state.st2 ; CLK      ;
; N/A   ; None         ; -0.304 ns  ; D[6] ; REGL[6]           ; CLK      ;
; N/A   ; None         ; -0.359 ns  ; D[7] ; REGL[7]           ; CLK      ;
; N/A   ; None         ; -0.359 ns  ; D[3] ; REGL[3]           ; CLK      ;
; N/A   ; None         ; -0.477 ns  ; D[0] ; REGL[0]           ; CLK      ;
; N/A   ; None         ; -0.518 ns  ; D[2] ; REGL[2]           ; CLK      ;
; N/A   ; None         ; -0.991 ns  ; D[4] ; REGL[4]           ; CLK      ;
; N/A   ; None         ; -0.995 ns  ; D[5] ; REGL[5]           ; CLK      ;
; N/A   ; None         ; -0.995 ns  ; D[1] ; REGL[1]           ; CLK      ;
+-------+--------------+------------+------+-------------------+----------+