?? small.fit.rpt.htm
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<H1>Fitter report for small</H1>
<H3>Wed Apr 20 20:12:42 2005<BR>
Version 5.0 Build 146 04/13/2005 SJ Full Version</H3>
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<P><HR></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Table of Contents</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<OL>
<LI><A HREF="#1">Legal Notice</A></LI>
<LI><A HREF="#2">Fitter Summary</A></LI>
<LI><A HREF="#3">Fitter Settings</A></LI>
<LI><A HREF="#4">Fitter Device Options</A></LI>
<LI><A HREF="#5">Fitter Equations</A></LI>
<LI><A HREF="#6">Pin-Out File</A></LI>
<LI><A HREF="#7">Fitter Resource Usage Summary</A></LI>
<LI><A HREF="#8">Input Pins</A></LI>
<LI><A HREF="#9">Output Pins</A></LI>
<LI><A HREF="#10">I/O Bank Usage</A></LI>
<LI><A HREF="#11">All Package Pins</A></LI>
<LI><A HREF="#12">Output Pin Default Load For Reported TCO</A></LI>
<LI><A HREF="#13">Fitter Resource Utilization by Entity</A></LI>
<LI><A HREF="#14">Delay Chain Summary</A></LI>
<LI><A HREF="#15">Pad To Core Delay Chain Fanout</A></LI>
<LI><A HREF="#16">Control Signals</A></LI>
<LI><A HREF="#17">Global & Other Fast Signals</A></LI>
<LI><A HREF="#18">Non-Global High Fan-Out Signals</A></LI>
<LI><A HREF="#19">Fitter RAM Summary</A></LI>
<LI><A HREF="#20">Interconnect Usage Summary</A></LI>
<LI><A HREF="#21">LAB Logic Elements</A></LI>
<LI><A HREF="#22">LAB-wide Signals</A></LI>
<LI><A HREF="#23">LAB Signals Sourced</A></LI>
<LI><A HREF="#24">LAB Signals Sourced Out</A></LI>
<LI><A HREF="#25">LAB Distinct Inputs</A></LI>
<LI><A HREF="#26">Fitter Messages</A></LI>
</OL>
<P><A NAME="1"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Legal Notice</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<PRE>Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
</PRE>
<P><A NAME="2"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Fitter Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle">
<TD ALIGN="LEFT">Fitter Status</TH>
<TD ALIGN="LEFT">Successful - Wed Apr 20 20:12:41 2005</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Quartus II Version</TD>
<TD ALIGN="LEFT">5.0 Build 146 04/13/2005 SJ Full Version</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Revision Name</TD>
<TD ALIGN="LEFT">small</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Top-level Entity Name</TD>
<TD ALIGN="LEFT">small</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Family</TD>
<TD ALIGN="LEFT">Cyclone II</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Device</TD>
<TD ALIGN="LEFT">EP2C35F672C6</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Timing Models</TD>
<TD ALIGN="LEFT">Preliminary</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total logic elements</TD>
<TD ALIGN="LEFT">583 / 33,216 ( 1 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total pins</TD>
<TD ALIGN="LEFT">10 / 475 ( 2 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total virtual pins</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total memory bits</TD>
<TD ALIGN="LEFT">17,408 / 483,840 ( 3 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Embedded Multiplier 9-bit elements</TD>
<TD ALIGN="LEFT">0 / 70 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total PLLs</TD>
<TD ALIGN="LEFT">0 / 4 ( 0 % )</TD>
</TR>
</TABLE>
<P><A NAME="3"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Fitter Settings</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Option</TH>
<TH>Setting</TH>
<TH>Default Value</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Device</TD>
<TD ALIGN="LEFT">EP2C35F672C6</TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Use smart compilation</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Placement Effort Multiplier</TD>
<TD ALIGN="LEFT">1.0</TD>
<TD ALIGN="LEFT">1.0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Router Effort Multiplier</TD>
<TD ALIGN="LEFT">1.0</TD>
<TD ALIGN="LEFT">1.0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Optimize Hold Timing</TD>
<TD ALIGN="LEFT">IO Paths and Minimum TPD Paths</TD>
<TD ALIGN="LEFT">IO Paths and Minimum TPD Paths</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Optimize Fast-Corner Timing</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Optimize Timing</TD>
<TD ALIGN="LEFT">Normal compilation</TD>
<TD ALIGN="LEFT">Normal compilation</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Optimize IOC Register Placement for Timing</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Limit to One Fitting Attempt</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Final Placement Optimizations</TD>
<TD ALIGN="LEFT">Automatically</TD>
<TD ALIGN="LEFT">Automatically</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Fitter Initial Placement Seed</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">1</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">PCI I/O</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Weak Pull-Up Resistor</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Enable Bus-Hold Circuitry</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Global Memory Control Signals</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Packed Registers -- Stratix II/Cyclone II</TD>
<TD ALIGN="LEFT">Auto</TD>
<TD ALIGN="LEFT">Auto</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Delay Chains</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Merge PLLs</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Fitter Effort</TD>
<TD ALIGN="LEFT">Auto Fit</TD>
<TD ALIGN="LEFT">Auto Fit</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Physical Synthesis Effort Level</TD>
<TD ALIGN="LEFT">Normal</TD>
<TD ALIGN="LEFT">Normal</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Global Clock</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto Global Register Control Signals</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
</TABLE>
<P><A NAME="4"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Fitter Device Options</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Option</TH>
<TH>Setting</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Enable user-supplied start-up clock (CLKUSR)</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Enable device-wide reset (DEV_CLRn)</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Enable device-wide output enable (DEV_OE) </TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Enable INIT_DONE output</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Configuration scheme</TD>
<TD ALIGN="LEFT">Active Serial</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Error detection CRC</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Reserve nCEO pin after configuration</TD>
<TD ALIGN="LEFT">As output driving ground</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Reserve all unused pins</TD>
<TD ALIGN="LEFT">As input tri-stated</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Base pin-out file on sameframe device</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
</TABLE>
<P><A NAME="5"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Fitter Equations</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<a href="file:///c:/Pabst/test_scratch/test/small/small.fit.eqn.htm">Fitter Equations</a><BR>
<P><A NAME="6"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Pin-Out File</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<a href="file:///c:/Pabst/test_scratch/test/small/small.pin">Pin-Out File</a><BR>
<P><A NAME="7"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Fitter Resource Usage Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Resource</TH>
<TH>Usage</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total logic elements</TD>
<TD ALIGN="LEFT">583 / 33,216 ( 1 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- Combinational with no register</TD>
<TD ALIGN="LEFT">277</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- Register only</TD>
<TD ALIGN="LEFT">27</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- Combinational with a register</TD>
<TD ALIGN="LEFT">279</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Logic element usage by number of LUT inputs</TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- 4 input functions</TD>
<TD ALIGN="LEFT">263</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- 3 input functions</TD>
<TD ALIGN="LEFT">250</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- <=2 input functions</TD>
<TD ALIGN="LEFT">43</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- Register only</TD>
<TD ALIGN="LEFT">27</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- Combinational cells for routing</TD>
<TD ALIGN="LEFT">24</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Logic elements by mode</TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- normal mode</TD>
<TD ALIGN="LEFT">480</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- arithmetic mode</TD>
<TD ALIGN="LEFT">76</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> </TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total registers</TD>
<TD ALIGN="LEFT">306 / 33,216 ( < 1 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total LABs</TD>
<TD ALIGN="LEFT">45 / 2,076 ( 2 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">User inserted logic elements </TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Virtual pins</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">I/O pins</TD>
<TD ALIGN="LEFT">10 / 475 ( 2 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- Clock pins </TD>
<TD ALIGN="LEFT">1 / 8 ( 12 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Global signals </TD>
<TD ALIGN="LEFT">2</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">M4Ks</TD>
<TD ALIGN="LEFT">6 / 105 ( 5 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total memory bits</TD>
<TD ALIGN="LEFT">17,408 / 483,840 ( 3 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total RAM block bits</TD>
<TD ALIGN="LEFT">27,648 / 483,840 ( 5 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Embedded Multiplier 9-bit elements</TD>
<TD ALIGN="LEFT">0 / 70 ( 0 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Global clocks</TD>
<TD ALIGN="LEFT">2 / 16 ( 12 % )</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maximum fan-out node</TD>
<TD ALIGN="LEFT">osc_clk[0]~clkctrl</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maximum fan-out</TD>
<TD ALIGN="LEFT">312</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total fan-out</TD>
<TD ALIGN="LEFT">3305</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Average fan-out</TD>
<TD ALIGN="LEFT">3.64</TD>
</TR>
</TABLE>
<P><A NAME="8"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Input Pins</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Name</TH>
<TH>Pin #</TH>
<TH>I/O Bank</TH>
<TH>X coordinate</TH>
<TH>Y coordinate</TH>
<TH>Cell number</TH>
<TH>Combinational Fan-Out</TH>
<TH>Registered Fan-Out</TH>
<TH>Global</TH>
<TH>Input Register</TH>
<TH>Power Up High</TH>
<TH>PCI I/O Enabled</TH>
<TH>Bus Hold</TH>
<TH>Weak Pull Up</TH>
<TH>I/O Standard</TH>
<TH>Termination</TH>
<TH>Location assigned by</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">osc_clk[0]</TD>
<TD ALIGN="LEFT">P25</TD>
<TD ALIGN="LEFT">6</TD>
<TD ALIGN="LEFT">65</TD>
<TD ALIGN="LEFT">19</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">no</TD>
<TD ALIGN="LEFT">no</TD>
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