|small
Q <= DFFLOP:inst3.Q
D => DFFLOP:inst3.D
D => TFFLOP:inst4.T
osc_clk[0] => dividef:inst2.CLK
osc_clk[0] => small_2C35:inst.clk
CLR => DFFLOP:inst3.CLR
PSET => DFFLOP:inst3.PSET
QT <= TFFLOP:inst4.QT
out_port_from_the_led_pio[0] <= inst1[0].DB_MAX_OUTPUT_PORT_TYPE
out_port_from_the_led_pio[1] <= inst1[1].DB_MAX_OUTPUT_PORT_TYPE
out_port_from_the_led_pio[2] <= inst1[2].DB_MAX_OUTPUT_PORT_TYPE
out_port_from_the_led_pio[3] <= inst1[3].DB_MAX_OUTPUT_PORT_TYPE
out_port_from_the_led_pio[4] <= inst1[4].DB_MAX_OUTPUT_PORT_TYPE
out_port_from_the_led_pio[5] <= inst1[5].DB_MAX_OUTPUT_PORT_TYPE
out_port_from_the_led_pio[6] <= inst1[6].DB_MAX_OUTPUT_PORT_TYPE
out_port_from_the_led_pio[7] <= inst1[7].DB_MAX_OUTPUT_PORT_TYPE
pld_clear_n => small_2C35:inst.reset_n


|small|DFFLOP:inst3
D => Q~reg0.DATAIN
CLK => Q~reg0.CLK
CLR => Q~0.IN1
PSET => Q~0.IN0
PSET => comb~0.IN0
PSET => comb~1.IN0
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE


|small|dividef:inst2
CLK => COUNT[24].CLK
CLK => COUNT[23].CLK
CLK => COUNT[22].CLK
CLK => COUNT[21].CLK
CLK => COUNT[20].CLK
CLK => COUNT[19].CLK
CLK => COUNT[18].CLK
CLK => COUNT[17].CLK
CLK => COUNT[16].CLK
CLK => COUNT[15].CLK
CLK => COUNT[14].CLK
CLK => COUNT[13].CLK
CLK => COUNT[12].CLK
CLK => COUNT[11].CLK
CLK => COUNT[10].CLK
CLK => COUNT[9].CLK
CLK => COUNT[8].CLK
CLK => COUNT[7].CLK
CLK => COUNT[6].CLK
CLK => COUNT[5].CLK
CLK => COUNT[4].CLK
CLK => COUNT[3].CLK
CLK => COUNT[2].CLK
CLK => COUNT[1].CLK
CLK => COUNT[0].CLK
CLK => COUNT[25].CLK
CLK_D <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE


|small|TFFLOP:inst4
T => Q_S.ENA
CLK => Q_S.CLK
QT <= Q_S.DB_MAX_OUTPUT_PORT_TYPE


|small|small_2C35:inst
clk => small_2C35_reset_clk_domain_synch_module:small_2C35_reset_clk_domain_synch.clk
clk => onchip_ram:the_onchip_ram.clk
clk => onchip_ram_s1_arbitrator:the_onchip_ram_s1.clk
clk => led_pio:the_led_pio.clk
clk => led_pio_s1_arbitrator:the_led_pio_s1.clk
clk => cpu:the_cpu.clk
clk => cpu_instruction_master_arbitrator:the_cpu_instruction_master.clk
clk => cpu_data_master_arbitrator:the_cpu_data_master.clk
reset_n => small_2C35_reset_clk_domain_synch_module:small_2C35_reset_clk_domain_synch.reset_n
out_port_from_the_led_pio[0] <= led_pio:the_led_pio.out_port[0]
out_port_from_the_led_pio[1] <= led_pio:the_led_pio.out_port[1]
out_port_from_the_led_pio[2] <= led_pio:the_led_pio.out_port[2]
out_port_from_the_led_pio[3] <= led_pio:the_led_pio.out_port[3]
out_port_from_the_led_pio[4] <= led_pio:the_led_pio.out_port[4]
out_port_from_the_led_pio[5] <= led_pio:the_led_pio.out_port[5]
out_port_from_the_led_pio[6] <= led_pio:the_led_pio.out_port[6]
out_port_from_the_led_pio[7] <= led_pio:the_led_pio.out_port[7]


|small|small_2C35:inst|cpu_data_master_arbitrator:the_cpu_data_master
clk => internal_cpu_data_master_waitrequest.CLK
cpu_data_master_address[0] => cpu_data_master_address_to_slave[0].DATAIN
cpu_data_master_address[1] => cpu_data_master_address_to_slave[1].DATAIN
cpu_data_master_address[2] => cpu_data_master_address_to_slave[2].DATAIN
cpu_data_master_address[3] => cpu_data_master_address_to_slave[3].DATAIN
cpu_data_master_address[4] => cpu_data_master_address_to_slave[4].DATAIN
cpu_data_master_address[5] => cpu_data_master_address_to_slave[5].DATAIN
cpu_data_master_address[6] => cpu_data_master_address_to_slave[6].DATAIN
cpu_data_master_address[7] => cpu_data_master_address_to_slave[7].DATAIN
cpu_data_master_address[8] => cpu_data_master_address_to_slave[8].DATAIN
cpu_data_master_address[9] => cpu_data_master_address_to_slave[9].DATAIN
cpu_data_master_address[10] => cpu_data_master_address_to_slave[10].DATAIN
cpu_data_master_address[11] => ~NO_FANOUT~
cpu_data_master_address[12] => ~NO_FANOUT~
cpu_data_master_address[13] => ~NO_FANOUT~
cpu_data_master_address[14] => cpu_data_master_address_to_slave[14].DATAIN
cpu_data_master_granted_led_pio_s1 => ~NO_FANOUT~
cpu_data_master_granted_onchip_ram_s1 => r_0~10.IN1
cpu_data_master_qualified_request_led_pio_s1 => r_0~0.IN0
cpu_data_master_qualified_request_led_pio_s1 => r_0~1.IN0
cpu_data_master_qualified_request_led_pio_s1 => r_0~4.IN0
cpu_data_master_qualified_request_onchip_ram_s1 => r_0~7.IN0
cpu_data_master_qualified_request_onchip_ram_s1 => r_0~10.IN0
cpu_data_master_qualified_request_onchip_ram_s1 => r_0~12.IN1
cpu_data_master_qualified_request_onchip_ram_s1 => r_0~16.IN1
cpu_data_master_read => r_0~2.IN0
cpu_data_master_read => r_0~13.IN0
cpu_data_master_read => internal_cpu_data_master_waitrequest~0.IN0
cpu_data_master_read => r_0~1.IN1
cpu_data_master_read => r_0~12.IN0
cpu_data_master_read_data_valid_led_pio_s1 => ~NO_FANOUT~
cpu_data_master_read_data_valid_onchip_ram_s1 => ~NO_FANOUT~
cpu_data_master_requests_led_pio_s1 => r_0~0.IN1
cpu_data_master_requests_onchip_ram_s1 => r_0~8.IN1
cpu_data_master_write => r_0~5.IN0
cpu_data_master_write => r_0~17.IN0
cpu_data_master_write => internal_cpu_data_master_waitrequest~0.IN1
cpu_data_master_write => r_0~4.IN1
cpu_data_master_write => r_0~16.IN0
d1_led_pio_s1_end_xfer => ~NO_FANOUT~
d1_onchip_ram_s1_end_xfer => ~NO_FANOUT~
onchip_ram_s1_readdata_from_sa[0] => cpu_data_master_readdata[0].DATAIN
onchip_ram_s1_readdata_from_sa[1] => cpu_data_master_readdata[1].DATAIN
onchip_ram_s1_readdata_from_sa[2] => cpu_data_master_readdata[2].DATAIN
onchip_ram_s1_readdata_from_sa[3] => cpu_data_master_readdata[3].DATAIN
onchip_ram_s1_readdata_from_sa[4] => cpu_data_master_readdata[4].DATAIN
onchip_ram_s1_readdata_from_sa[5] => cpu_data_master_readdata[5].DATAIN
onchip_ram_s1_readdata_from_sa[6] => cpu_data_master_readdata[6].DATAIN
onchip_ram_s1_readdata_from_sa[7] => cpu_data_master_readdata[7].DATAIN
onchip_ram_s1_readdata_from_sa[8] => cpu_data_master_readdata[8].DATAIN
onchip_ram_s1_readdata_from_sa[9] => cpu_data_master_readdata[9].DATAIN
onchip_ram_s1_readdata_from_sa[10] => cpu_data_master_readdata[10].DATAIN
onchip_ram_s1_readdata_from_sa[11] => cpu_data_master_readdata[11].DATAIN
onchip_ram_s1_readdata_from_sa[12] => cpu_data_master_readdata[12].DATAIN
onchip_ram_s1_readdata_from_sa[13] => cpu_data_master_readdata[13].DATAIN
onchip_ram_s1_readdata_from_sa[14] => cpu_data_master_readdata[14].DATAIN
onchip_ram_s1_readdata_from_sa[15] => cpu_data_master_readdata[15].DATAIN
onchip_ram_s1_readdata_from_sa[16] => cpu_data_master_readdata[16].DATAIN
onchip_ram_s1_readdata_from_sa[17] => cpu_data_master_readdata[17].DATAIN
onchip_ram_s1_readdata_from_sa[18] => cpu_data_master_readdata[18].DATAIN
onchip_ram_s1_readdata_from_sa[19] => cpu_data_master_readdata[19].DATAIN
onchip_ram_s1_readdata_from_sa[20] => cpu_data_master_readdata[20].DATAIN
onchip_ram_s1_readdata_from_sa[21] => cpu_data_master_readdata[21].DATAIN
onchip_ram_s1_readdata_from_sa[22] => cpu_data_master_readdata[22].DATAIN
onchip_ram_s1_readdata_from_sa[23] => cpu_data_master_readdata[23].DATAIN
onchip_ram_s1_readdata_from_sa[24] => cpu_data_master_readdata[24].DATAIN
onchip_ram_s1_readdata_from_sa[25] => cpu_data_master_readdata[25].DATAIN
onchip_ram_s1_readdata_from_sa[26] => cpu_data_master_readdata[26].DATAIN
onchip_ram_s1_readdata_from_sa[27] => cpu_data_master_readdata[27].DATAIN
onchip_ram_s1_readdata_from_sa[28] => cpu_data_master_readdata[28].DATAIN
onchip_ram_s1_readdata_from_sa[29] => cpu_data_master_readdata[29].DATAIN
onchip_ram_s1_readdata_from_sa[30] => cpu_data_master_readdata[30].DATAIN
onchip_ram_s1_readdata_from_sa[31] => cpu_data_master_readdata[31].DATAIN
registered_cpu_data_master_read_data_valid_onchip_ram_s1 => r_0~7.IN1
registered_cpu_data_master_read_data_valid_onchip_ram_s1 => r_0~13.IN1
reset_n => cpu_data_master_reset_n.DATAIN
reset_n => internal_cpu_data_master_waitrequest.PRESET
cpu_data_master_address_to_slave[0] <= cpu_data_master_address[0].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_address_to_slave[1] <= cpu_data_master_address[1].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_address_to_slave[2] <= cpu_data_master_address[2].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_address_to_slave[3] <= cpu_data_master_address[3].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_address_to_slave[4] <= cpu_data_master_address[4].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_address_to_slave[5] <= cpu_data_master_address[5].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_address_to_slave[6] <= cpu_data_master_address[6].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_address_to_slave[7] <= cpu_data_master_address[7].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_address_to_slave[8] <= cpu_data_master_address[8].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_address_to_slave[9] <= cpu_data_master_address[9].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_address_to_slave[10] <= cpu_data_master_address[10].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_address_to_slave[11] <= <GND>
cpu_data_master_address_to_slave[12] <= <GND>
cpu_data_master_address_to_slave[13] <= <GND>
cpu_data_master_address_to_slave[14] <= cpu_data_master_address[14].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[0] <= onchip_ram_s1_readdata_from_sa[0].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[1] <= onchip_ram_s1_readdata_from_sa[1].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[2] <= onchip_ram_s1_readdata_from_sa[2].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[3] <= onchip_ram_s1_readdata_from_sa[3].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[4] <= onchip_ram_s1_readdata_from_sa[4].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[5] <= onchip_ram_s1_readdata_from_sa[5].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[6] <= onchip_ram_s1_readdata_from_sa[6].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[7] <= onchip_ram_s1_readdata_from_sa[7].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[8] <= onchip_ram_s1_readdata_from_sa[8].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[9] <= onchip_ram_s1_readdata_from_sa[9].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[10] <= onchip_ram_s1_readdata_from_sa[10].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[11] <= onchip_ram_s1_readdata_from_sa[11].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[12] <= onchip_ram_s1_readdata_from_sa[12].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[13] <= onchip_ram_s1_readdata_from_sa[13].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[14] <= onchip_ram_s1_readdata_from_sa[14].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[15] <= onchip_ram_s1_readdata_from_sa[15].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[16] <= onchip_ram_s1_readdata_from_sa[16].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[17] <= onchip_ram_s1_readdata_from_sa[17].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[18] <= onchip_ram_s1_readdata_from_sa[18].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[19] <= onchip_ram_s1_readdata_from_sa[19].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[20] <= onchip_ram_s1_readdata_from_sa[20].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[21] <= onchip_ram_s1_readdata_from_sa[21].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[22] <= onchip_ram_s1_readdata_from_sa[22].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[23] <= onchip_ram_s1_readdata_from_sa[23].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[24] <= onchip_ram_s1_readdata_from_sa[24].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[25] <= onchip_ram_s1_readdata_from_sa[25].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[26] <= onchip_ram_s1_readdata_from_sa[26].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[27] <= onchip_ram_s1_readdata_from_sa[27].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[28] <= onchip_ram_s1_readdata_from_sa[28].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[29] <= onchip_ram_s1_readdata_from_sa[29].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[30] <= onchip_ram_s1_readdata_from_sa[30].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_readdata[31] <= onchip_ram_s1_readdata_from_sa[31].DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_reset_n <= reset_n.DB_MAX_OUTPUT_PORT_TYPE
cpu_data_master_waitrequest <= internal_cpu_data_master_waitrequest.DB_MAX_OUTPUT_PORT_TYPE


|small|small_2C35:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master
clk => ~NO_FANOUT~
cpu_instruction_master_address[0] => cpu_instruction_master_address_to_slave[0].DATAIN
cpu_instruction_master_address[1] => cpu_instruction_master_address_to_slave[1].DATAIN
cpu_instruction_master_address[2] => cpu_instruction_master_address_to_slave[2].DATAIN
cpu_instruction_master_address[3] => cpu_instruction_master_address_to_slave[3].DATAIN
cpu_instruction_master_address[4] => cpu_instruction_master_address_to_slave[4].DATAIN
cpu_instruction_master_address[5] => cpu_instruction_master_address_to_slave[5].DATAIN
cpu_instruction_master_address[6] => cpu_instruction_master_address_to_slave[6].DATAIN
cpu_instruction_master_address[7] => cpu_instruction_master_address_to_slave[7].DATAIN
cpu_instruction_master_address[8] => cpu_instruction_master_address_to_slave[8].DATAIN
cpu_instruction_master_address[9] => cpu_instruction_master_address_to_slave[9].DATAIN
cpu_instruction_master_address[10] => cpu_instruction_master_address_to_slave[10].DATAIN
cpu_instruction_master_granted_onchip_ram_s1 => r_0~2.IN1
cpu_instruction_master_qualified_request_onchip_ram_s1 => r_0~0.IN0
cpu_instruction_master_qualified_request_onchip_ram_s1 => r_0~2.IN0
cpu_instruction_master_qualified_request_onchip_ram_s1 => r_0~4.IN0
cpu_instruction_master_read => r_0~5.IN1
cpu_instruction_master_read => r_0~4.IN1
cpu_instruction_master_read_data_valid_onchip_ram_s1 => r_0~0.IN1
cpu_instruction_master_read_data_valid_onchip_ram_s1 => r_0~5.IN0
cpu_instruction_master_requests_onchip_ram_s1 => r_0~1.IN1
d1_onchip_ram_s1_end_xfer => ~NO_FANOUT~
onchip_ram_s1_readdata_from_sa[0] => cpu_instruction_master_readdata[0].DATAIN
onchip_ram_s1_readdata_from_sa[1] => cpu_instruction_master_readdata[1].DATAIN
onchip_ram_s1_readdata_from_sa[2] => cpu_instruction_master_readdata[2].DATAIN
onchip_ram_s1_readdata_from_sa[3] => cpu_instruction_master_readdata[3].DATAIN
onchip_ram_s1_readdata_from_sa[4] => cpu_instruction_master_readdata[4].DATAIN
onchip_ram_s1_readdata_from_sa[5] => cpu_instruction_master_readdata[5].DATAIN
onchip_ram_s1_readdata_from_sa[6] => cpu_instruction_master_readdata[6].DATAIN
onchip_ram_s1_readdata_from_sa[7] => cpu_instruction_master_readdata[7].DATAIN
onchip_ram_s1_readdata_from_sa[8] => cpu_instruction_master_readdata[8].DATAIN
onchip_ram_s1_readdata_from_sa[9] => cpu_instruction_master_readdata[9].DATAIN
onchip_ram_s1_readdata_from_sa[10] => cpu_instruction_master_readdata[10].DATAIN
onchip_ram_s1_readdata_from_sa[11] => cpu_instruction_master_readdata[11].DATAIN
onchip_ram_s1_readdata_from_sa[12] => cpu_instruction_master_readdata[12].DATAIN
onchip_ram_s1_readdata_from_sa[13] => cpu_instruction_master_readdata[13].DATAIN
onchip_ram_s1_readdata_from_sa[14] => cpu_instruction_master_readdata[14].DATAIN
onchip_ram_s1_readdata_from_sa[15] => cpu_instruction_master_readdata[15].DATAIN
onchip_ram_s1_readdata_from_sa[16] => cpu_instruction_master_readdata[16].DATAIN
onchip_ram_s1_readdata_from_sa[17] => cpu_instruction_master_readdata[17].DATAIN
onchip_ram_s1_readdata_from_sa[18] => cpu_instruction_master_readdata[18].DATAIN
onchip_ram_s1_readdata_from_sa[19] => cpu_instruction_master_readdata[19].DATAIN
onchip_ram_s1_readdata_from_sa[20] => cpu_instruction_master_readdata[20].DATAIN
onchip_ram_s1_readdata_from_sa[21] => cpu_instruction_master_readdata[21].DATAIN
onchip_ram_s1_readdata_from_sa[22] => cpu_instruction_master_readdata[22].DATAIN
onchip_ram_s1_readdata_from_sa[23] => cpu_instruction_master_readdata[23].DATAIN
onchip_ram_s1_readdata_from_sa[24] => cpu_instruction_master_readdata[24].DATAIN
onchip_ram_s1_readdata_from_sa[25] => cpu_instruction_master_readdata[25].DATAIN
onchip_ram_s1_readdata_from_sa[26] => cpu_instruction_master_readdata[26].DATAIN
onchip_ram_s1_readdata_from_sa[27] => cpu_instruction_master_readdata[27].DATAIN
onchip_ram_s1_readdata_from_sa[28] => cpu_instruction_master_readdata[28].DATAIN
onchip_ram_s1_readdata_from_sa[29] => cpu_instruction_master_readdata[29].DATAIN
onchip_ram_s1_readdata_from_sa[30] => cpu_instruction_master_readdata[30].DATAIN
onchip_ram_s1_readdata_from_sa[31] => cpu_instruction_master_readdata[31].DATAIN
reset_n => ~NO_FANOUT~
cpu_instruction_master_address_to_slave[0] <= cpu_instruction_master_address[0].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_address_to_slave[1] <= cpu_instruction_master_address[1].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_address_to_slave[2] <= cpu_instruction_master_address[2].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_address_to_slave[3] <= cpu_instruction_master_address[3].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_address_to_slave[4] <= cpu_instruction_master_address[4].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_address_to_slave[5] <= cpu_instruction_master_address[5].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_address_to_slave[6] <= cpu_instruction_master_address[6].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_address_to_slave[7] <= cpu_instruction_master_address[7].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_address_to_slave[8] <= cpu_instruction_master_address[8].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_address_to_slave[9] <= cpu_instruction_master_address[9].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_address_to_slave[10] <= cpu_instruction_master_address[10].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[0] <= onchip_ram_s1_readdata_from_sa[0].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[1] <= onchip_ram_s1_readdata_from_sa[1].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[2] <= onchip_ram_s1_readdata_from_sa[2].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[3] <= onchip_ram_s1_readdata_from_sa[3].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[4] <= onchip_ram_s1_readdata_from_sa[4].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[5] <= onchip_ram_s1_readdata_from_sa[5].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[6] <= onchip_ram_s1_readdata_from_sa[6].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[7] <= onchip_ram_s1_readdata_from_sa[7].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[8] <= onchip_ram_s1_readdata_from_sa[8].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[9] <= onchip_ram_s1_readdata_from_sa[9].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[10] <= onchip_ram_s1_readdata_from_sa[10].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[11] <= onchip_ram_s1_readdata_from_sa[11].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[12] <= onchip_ram_s1_readdata_from_sa[12].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[13] <= onchip_ram_s1_readdata_from_sa[13].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[14] <= onchip_ram_s1_readdata_from_sa[14].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[15] <= onchip_ram_s1_readdata_from_sa[15].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[16] <= onchip_ram_s1_readdata_from_sa[16].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[17] <= onchip_ram_s1_readdata_from_sa[17].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[18] <= onchip_ram_s1_readdata_from_sa[18].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[19] <= onchip_ram_s1_readdata_from_sa[19].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[20] <= onchip_ram_s1_readdata_from_sa[20].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[21] <= onchip_ram_s1_readdata_from_sa[21].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[22] <= onchip_ram_s1_readdata_from_sa[22].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[23] <= onchip_ram_s1_readdata_from_sa[23].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[24] <= onchip_ram_s1_readdata_from_sa[24].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[25] <= onchip_ram_s1_readdata_from_sa[25].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[26] <= onchip_ram_s1_readdata_from_sa[26].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[27] <= onchip_ram_s1_readdata_from_sa[27].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[28] <= onchip_ram_s1_readdata_from_sa[28].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[29] <= onchip_ram_s1_readdata_from_sa[29].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[30] <= onchip_ram_s1_readdata_from_sa[30].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_readdata[31] <= onchip_ram_s1_readdata_from_sa[31].DB_MAX_OUTPUT_PORT_TYPE
cpu_instruction_master_waitrequest <= r_0.DB_MAX_OUTPUT_PORT_TYPE


|small|small_2C35:inst|cpu:the_cpu
clk => F_pc[7].CLK
clk => F_pc[6].CLK