clk => W_ipending_reg[11].CLK
clk => W_ipending_reg[10].CLK
clk => W_ipending_reg[9].CLK
clk => W_ipending_reg[8].CLK
clk => W_ipending_reg[7].CLK
clk => W_ipending_reg[6].CLK
clk => W_ipending_reg[5].CLK
clk => W_ipending_reg[4].CLK
clk => W_ipending_reg[3].CLK
clk => W_ipending_reg[2].CLK
clk => W_ipending_reg[1].CLK
clk => W_ipending_reg[0].CLK
clk => R_ctrl_br.CLK
clk => R_ctrl_jmp_direct.CLK
clk => R_ctrl_exception.CLK
clk => R_ctrl_break.CLK
clk => R_ctrl_uncond_cti.CLK
clk => R_ctrl_hi_imm.CLK
clk => R_ctrl_unsigned_lo_imm.CLK
clk => R_ctrl_force_src2_zero.CLK
clk => R_ctrl_retaddr.CLK
clk => R_ctrl_dst_data_sel_cmp.CLK
clk => R_ctrl_dst_data_sel_logic_result.CLK
clk => R_ctrl_wrctl_inst.CLK
clk => R_ctrl_rdctl_inst.CLK
clk => R_ctrl_ld.CLK
clk => R_ctrl_ld_signed.CLK
clk => R_ctrl_ld_non_io.CLK
clk => R_ctrl_st.CLK
clk => R_ctrl_shift_rot.CLK
clk => R_ctrl_rot_right.CLK
clk => R_ctrl_shift_logical.CLK
clk => R_ctrl_shift_rot_right.CLK
clk => cpu_rf_module:cpu_rf.clock1
clk => cpu_rf_module:cpu_rf.clock0
clk => cpu_test_bench:the_cpu_test_bench.clk
clk => F_pc[8].CLK
d_irq[0] => ~NO_FANOUT~
d_irq[1] => ~NO_FANOUT~
d_irq[2] => ~NO_FANOUT~
d_irq[3] => ~NO_FANOUT~
d_irq[4] => ~NO_FANOUT~
d_irq[5] => ~NO_FANOUT~
d_irq[6] => ~NO_FANOUT~
d_irq[7] => ~NO_FANOUT~
d_irq[8] => ~NO_FANOUT~
d_irq[9] => ~NO_FANOUT~
d_irq[10] => ~NO_FANOUT~
d_irq[11] => ~NO_FANOUT~
d_irq[12] => ~NO_FANOUT~
d_irq[13] => ~NO_FANOUT~
d_irq[14] => ~NO_FANOUT~
d_irq[15] => ~NO_FANOUT~
d_irq[16] => ~NO_FANOUT~
d_irq[17] => ~NO_FANOUT~
d_irq[18] => ~NO_FANOUT~
d_irq[19] => ~NO_FANOUT~
d_irq[20] => ~NO_FANOUT~
d_irq[21] => ~NO_FANOUT~
d_irq[22] => ~NO_FANOUT~
d_irq[23] => ~NO_FANOUT~
d_irq[24] => ~NO_FANOUT~
d_irq[25] => ~NO_FANOUT~
d_irq[26] => ~NO_FANOUT~
d_irq[27] => ~NO_FANOUT~
d_irq[28] => ~NO_FANOUT~
d_irq[29] => ~NO_FANOUT~
d_irq[30] => ~NO_FANOUT~
d_irq[31] => ~NO_FANOUT~
d_readdata[0] => A_WE_StdLogicVector~339.DATAA
d_readdata[1] => A_WE_StdLogicVector~338.DATAA
d_readdata[2] => A_WE_StdLogicVector~337.DATAA
d_readdata[3] => A_WE_StdLogicVector~336.DATAA
d_readdata[4] => A_WE_StdLogicVector~335.DATAA
d_readdata[5] => A_WE_StdLogicVector~334.DATAA
d_readdata[6] => A_WE_StdLogicVector~333.DATAA
d_readdata[7] => A_WE_StdLogicVector~332.DATAA
d_readdata[8] => A_WE_StdLogicVector~347.DATAA
d_readdata[9] => A_WE_StdLogicVector~346.DATAA
d_readdata[10] => A_WE_StdLogicVector~345.DATAA
d_readdata[11] => A_WE_StdLogicVector~344.DATAA
d_readdata[12] => A_WE_StdLogicVector~343.DATAA
d_readdata[13] => A_WE_StdLogicVector~342.DATAA
d_readdata[14] => A_WE_StdLogicVector~341.DATAA
d_readdata[15] => A_WE_StdLogicVector~340.DATAA
d_readdata[16] => A_WE_StdLogicVector~355.DATAA
d_readdata[17] => A_WE_StdLogicVector~354.DATAA
d_readdata[18] => A_WE_StdLogicVector~353.DATAA
d_readdata[19] => A_WE_StdLogicVector~352.DATAA
d_readdata[20] => A_WE_StdLogicVector~351.DATAA
d_readdata[21] => A_WE_StdLogicVector~350.DATAA
d_readdata[22] => A_WE_StdLogicVector~349.DATAA
d_readdata[23] => A_WE_StdLogicVector~348.DATAA
d_readdata[24] => A_WE_StdLogicVector~363.DATAA
d_readdata[25] => A_WE_StdLogicVector~362.DATAA
d_readdata[26] => A_WE_StdLogicVector~361.DATAA
d_readdata[27] => A_WE_StdLogicVector~360.DATAA
d_readdata[28] => A_WE_StdLogicVector~359.DATAA
d_readdata[29] => A_WE_StdLogicVector~358.DATAA
d_readdata[30] => A_WE_StdLogicVector~357.DATAA
d_readdata[31] => A_WE_StdLogicVector~356.DATAA
d_waitrequest => d_read_nxt~1.IN1
d_waitrequest => d_write_nxt~1.IN1
d_waitrequest => av_ld_getting_data.IN1
i_readdata[0] => A_WE_StdLogicVector~50.DATAA
i_readdata[0] => cpu_test_bench:the_cpu_test_bench.i_readdata[0]
i_readdata[1] => A_WE_StdLogicVector~49.DATAA
i_readdata[1] => cpu_test_bench:the_cpu_test_bench.i_readdata[1]
i_readdata[2] => A_WE_StdLogicVector~48.DATAA
i_readdata[2] => cpu_test_bench:the_cpu_test_bench.i_readdata[2]
i_readdata[3] => A_WE_StdLogicVector~47.DATAA
i_readdata[3] => cpu_test_bench:the_cpu_test_bench.i_readdata[3]
i_readdata[4] => A_WE_StdLogicVector~46.DATAA
i_readdata[4] => cpu_test_bench:the_cpu_test_bench.i_readdata[4]
i_readdata[5] => A_WE_StdLogicVector~45.DATAA
i_readdata[5] => cpu_test_bench:the_cpu_test_bench.i_readdata[5]
i_readdata[6] => A_WE_StdLogicVector~44.DATAA
i_readdata[6] => cpu_test_bench:the_cpu_test_bench.i_readdata[6]
i_readdata[7] => A_WE_StdLogicVector~43.DATAA
i_readdata[7] => cpu_test_bench:the_cpu_test_bench.i_readdata[7]
i_readdata[8] => A_WE_StdLogicVector~42.DATAA
i_readdata[8] => cpu_test_bench:the_cpu_test_bench.i_readdata[8]
i_readdata[9] => A_WE_StdLogicVector~41.DATAA
i_readdata[9] => cpu_test_bench:the_cpu_test_bench.i_readdata[9]
i_readdata[10] => A_WE_StdLogicVector~40.DATAA
i_readdata[10] => cpu_test_bench:the_cpu_test_bench.i_readdata[10]
i_readdata[11] => A_WE_StdLogicVector~39.DATAA
i_readdata[11] => cpu_test_bench:the_cpu_test_bench.i_readdata[11]
i_readdata[12] => A_WE_StdLogicVector~38.DATAA
i_readdata[12] => cpu_test_bench:the_cpu_test_bench.i_readdata[12]
i_readdata[13] => A_WE_StdLogicVector~37.DATAA
i_readdata[13] => cpu_test_bench:the_cpu_test_bench.i_readdata[13]
i_readdata[14] => A_WE_StdLogicVector~36.DATAA
i_readdata[14] => cpu_test_bench:the_cpu_test_bench.i_readdata[14]
i_readdata[15] => A_WE_StdLogicVector~35.DATAA
i_readdata[15] => cpu_test_bench:the_cpu_test_bench.i_readdata[15]
i_readdata[16] => A_WE_StdLogicVector~34.DATAA
i_readdata[16] => cpu_test_bench:the_cpu_test_bench.i_readdata[16]
i_readdata[17] => A_WE_StdLogicVector~33.DATAA
i_readdata[17] => cpu_test_bench:the_cpu_test_bench.i_readdata[17]
i_readdata[18] => A_WE_StdLogicVector~32.DATAA
i_readdata[18] => cpu_test_bench:the_cpu_test_bench.i_readdata[18]
i_readdata[19] => A_WE_StdLogicVector~31.DATAA
i_readdata[19] => cpu_test_bench:the_cpu_test_bench.i_readdata[19]
i_readdata[20] => A_WE_StdLogicVector~30.DATAA
i_readdata[20] => cpu_test_bench:the_cpu_test_bench.i_readdata[20]
i_readdata[21] => A_WE_StdLogicVector~29.DATAA
i_readdata[21] => cpu_test_bench:the_cpu_test_bench.i_readdata[21]
i_readdata[22] => A_WE_StdLogicVector~28.DATAA
i_readdata[22] => cpu_test_bench:the_cpu_test_bench.i_readdata[22]
i_readdata[23] => A_WE_StdLogicVector~27.DATAA
i_readdata[23] => cpu_test_bench:the_cpu_test_bench.i_readdata[23]
i_readdata[24] => A_WE_StdLogicVector~26.DATAA
i_readdata[24] => cpu_test_bench:the_cpu_test_bench.i_readdata[24]
i_readdata[25] => A_WE_StdLogicVector~25.DATAA
i_readdata[25] => cpu_test_bench:the_cpu_test_bench.i_readdata[25]
i_readdata[26] => A_WE_StdLogicVector~24.DATAA
i_readdata[26] => cpu_test_bench:the_cpu_test_bench.i_readdata[26]
i_readdata[27] => A_WE_StdLogicVector~23.DATAA
i_readdata[27] => cpu_test_bench:the_cpu_test_bench.i_readdata[27]
i_readdata[28] => A_WE_StdLogicVector~22.DATAA
i_readdata[28] => cpu_test_bench:the_cpu_test_bench.i_readdata[28]
i_readdata[29] => A_WE_StdLogicVector~21.DATAA
i_readdata[29] => cpu_test_bench:the_cpu_test_bench.i_readdata[29]
i_readdata[30] => A_WE_StdLogicVector~20.DATAA
i_readdata[30] => cpu_test_bench:the_cpu_test_bench.i_readdata[30]
i_readdata[31] => A_WE_StdLogicVector~19.DATAA
i_readdata[31] => cpu_test_bench:the_cpu_test_bench.i_readdata[31]
i_waitrequest => i_read_nxt~0.IN1
i_waitrequest => cpu_test_bench:the_cpu_test_bench.i_waitrequest
i_waitrequest => F_valid.IN1
reset_n => cpu_test_bench:the_cpu_test_bench.reset_n
reset_n => W_rf_wren_a.IN0
reset_n => W_alu_result[30].ACLR
reset_n => W_alu_result[29].ACLR
reset_n => W_alu_result[28].ACLR
reset_n => W_alu_result[27].ACLR
reset_n => W_alu_result[26].ACLR
reset_n => W_alu_result[25].ACLR
reset_n => W_alu_result[24].ACLR
reset_n => W_alu_result[23].ACLR
reset_n => W_alu_result[22].ACLR
reset_n => W_alu_result[21].ACLR
reset_n => W_alu_result[20].ACLR
reset_n => W_alu_result[19].ACLR
reset_n => W_alu_result[18].ACLR
reset_n => W_alu_result[17].ACLR
reset_n => W_alu_result[16].ACLR
reset_n => W_alu_result[15].ACLR
reset_n => W_alu_result[14].ACLR
reset_n => W_alu_result[13].ACLR
reset_n => W_alu_result[12].ACLR
reset_n => W_alu_result[11].ACLR
reset_n => W_alu_result[10].ACLR
reset_n => W_alu_result[9].ACLR
reset_n => W_alu_result[8].ACLR
reset_n => W_alu_result[7].ACLR
reset_n => W_alu_result[6].ACLR
reset_n => W_alu_result[5].ACLR
reset_n => W_alu_result[4].ACLR
reset_n => W_alu_result[3].ACLR
reset_n => W_alu_result[2].ACLR
reset_n => W_alu_result[1].ACLR
reset_n => W_alu_result[0].ACLR
reset_n => internal_d_byteenable[2].ACLR
reset_n => W_alu_result[31].ACLR
reset_n => internal_d_byteenable[1].ACLR
reset_n => internal_d_byteenable[0].ACLR
reset_n => internal_d_byteenable[3].ACLR
reset_n => internal_d_read.ACLR
reset_n => d_writedata[30]~reg0.ACLR
reset_n => d_writedata[29]~reg0.ACLR
reset_n => d_writedata[28]~reg0.ACLR
reset_n => d_writedata[27]~reg0.ACLR
reset_n => d_writedata[26]~reg0.ACLR
reset_n => d_writedata[25]~reg0.ACLR
reset_n => d_writedata[24]~reg0.ACLR
reset_n => d_writedata[23]~reg0.ACLR
reset_n => d_writedata[22]~reg0.ACLR
reset_n => d_writedata[21]~reg0.ACLR
reset_n => d_writedata[20]~reg0.ACLR
reset_n => d_writedata[19]~reg0.ACLR
reset_n => d_writedata[18]~reg0.ACLR
reset_n => d_writedata[17]~reg0.ACLR
reset_n => d_writedata[16]~reg0.ACLR
reset_n => d_writedata[15]~reg0.ACLR
reset_n => d_writedata[14]~reg0.ACLR
reset_n => d_writedata[13]~reg0.ACLR
reset_n => d_writedata[12]~reg0.ACLR
reset_n => d_writedata[11]~reg0.ACLR
reset_n => d_writedata[10]~reg0.ACLR
reset_n => d_writedata[9]~reg0.ACLR
reset_n => d_writedata[8]~reg0.ACLR
reset_n => d_writedata[7]~reg0.ACLR
reset_n => d_writedata[6]~reg0.ACLR
reset_n => d_writedata[5]~reg0.ACLR
reset_n => d_writedata[4]~reg0.ACLR
reset_n => d_writedata[3]~reg0.ACLR
reset_n => d_writedata[2]~reg0.ACLR
reset_n => d_writedata[1]~reg0.ACLR
reset_n => d_writedata[0]~reg0.ACLR
reset_n => d_writedata[31]~reg0.ACLR
reset_n => F_pc[7].ACLR
reset_n => F_pc[6].ACLR
reset_n => F_pc[5].ACLR
reset_n => F_pc[4].ACLR
reset_n => F_pc[3].ACLR
reset_n => F_pc[2].ACLR
reset_n => F_pc[1].ACLR
reset_n => F_pc[0].ACLR
reset_n => F_pc[8].ACLR
reset_n => internal_i_read.PRESET
reset_n => D_iw[30].ACLR
reset_n => D_iw[29].ACLR
reset_n => D_iw[28].ACLR
reset_n => D_iw[27].ACLR
reset_n => D_iw[26].ACLR
reset_n => D_iw[25].ACLR
reset_n => D_iw[24].ACLR
reset_n => D_iw[23].ACLR
reset_n => D_iw[22].ACLR
reset_n => D_iw[21].ACLR
reset_n => D_iw[20].ACLR
reset_n => D_iw[19].ACLR
reset_n => D_iw[18].ACLR
reset_n => D_iw[17].ACLR
reset_n => D_iw[16].ACLR
reset_n => D_iw[15].ACLR
reset_n => D_iw[14].ACLR
reset_n => D_iw[13].ACLR
reset_n => D_iw[12].ACLR
reset_n => D_iw[11].ACLR
reset_n => D_iw[10].ACLR
reset_n => D_iw[9].ACLR
reset_n => D_iw[8].ACLR
reset_n => D_iw[7].ACLR
reset_n => D_iw[6].ACLR
reset_n => D_iw[5].ACLR
reset_n => D_iw[4].ACLR
reset_n => D_iw[3].ACLR
reset_n => D_iw[2].ACLR
reset_n => D_iw[1].ACLR
reset_n => D_iw[0].ACLR
reset_n => D_iw[31].ACLR
reset_n => D_valid.ACLR
reset_n => R_valid.ACLR
reset_n => R_wr_dst_reg.ACLR
reset_n => R_dst_regnum[3].ACLR
reset_n => R_dst_regnum[2].ACLR
reset_n => R_dst_regnum[1].ACLR
reset_n => R_dst_regnum[0].ACLR
reset_n => R_dst_regnum[4].ACLR
reset_n => R_logic_op[0].ACLR
reset_n => R_logic_op[1].ACLR
reset_n => R_compare_op[0].ACLR
reset_n => R_compare_op[1].ACLR
reset_n => R_src2_use_imm.ACLR
reset_n => E_valid.ACLR
reset_n => E_new_inst.ACLR
reset_n => E_src1[30].ACLR
reset_n => E_src1[29].ACLR
reset_n => E_src1[28].ACLR
reset_n => E_src1[27].ACLR
reset_n => E_src1[26].ACLR
reset_n => E_src1[25].ACLR
reset_n => E_src1[24].ACLR
reset_n => E_src1[23].ACLR
reset_n => E_src1[22].ACLR
reset_n => E_src1[21].ACLR
reset_n => E_src1[20].ACLR
reset_n => E_src1[19].ACLR
reset_n => E_src1[18].ACLR
reset_n => E_src1[17].ACLR
reset_n => E_src1[16].ACLR
reset_n => E_src1[15].ACLR
reset_n => E_src1[14].ACLR
reset_n => E_src1[13].ACLR
reset_n => E_src1[12].ACLR
reset_n => E_src1[11].ACLR
reset_n => E_src1[10].ACLR