module dpll(//input              clk,fin,reset,K,              //output              fout,fc2);input clk,fin,reset;input[3:0] K;output  fout,fc2;wire fout,fc2;wire hidclock,carryinc,borrowdec,nidout,xork;xorphd dpllxorphd(.fin(fin),                  .fout(fout),                  .se(xork));                  moKcounter dpllmoKcounter(.clk(clk),                          .se(xork),                          .K(K),                          .reset(reset),                          .carry(carryinc),                          .borrow(borrowdec));                                      maichongjiajian dpllmaichongjiajian(.IDCLOCK(hidclock),                                    .INC(carryinc),                                    .DEC(borrowdec),                                    .reset(reset),                                    .IDOUT(nidout));                                      divfrequency64 dplldivfrequency64(.IDOUT(nidout),                                   .reset(reset),                                   .fout(fout));                                                                divfrequency32 dplldivfrequency32(.IDOUT(nidout),                                  .reset(reset),                                  .fc2(fc2));                                                                   divfrequency8  dplldivfrequency8(.clk(clk),                                 .reset(reset),                                 .IDCLOCK(hidclock));                                endmodule