module divfrequency32(//input                     IDOUT,reset,                     //output                     fc2);    input IDOUT,reset;    output fc2;    wire fc2;    reg[4:0] count;      always @(posedge IDOUT or reset)     begin if(!reset) count=0;           else if(count==5'd31)  count=0;           else count=count+1;       end    assign  fc2=count[4];            endmodule