module divfrequency64(//input                       IDOUT,reset,                       //output                       fout);    input IDOUT,reset;    output fout;    wire fout;    reg[5:0] count;      always @(posedge IDOUT or reset)     begin if(!reset) count=0;           else if(count==6'd63)  count=0;           else count=count+1;                  end       assign fout=count[5];                  endmodule