module divfrequency8(//input                   clk,reset,                   //output                   IDCLOCK);    input clk,reset;    output IDCLOCK;   wire IDCLOCK;    reg[2:0] count;      always @(posedge clk or reset)     begin if(!reset) count=0;           else  count=count+1;              end       assign IDCLOCK=count[2];        endmodule