; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/Altera/myvhdl/myshizhong/myshizhong.pin.


+-------------------------------------------------------------------+
; Fitter Resource Usage Summary                                     ;
+---------------------------------------------+---------------------+
; Resource                                    ; Usage               ;
+---------------------------------------------+---------------------+
; Total logic elements                        ; 177 / 4,608 ( 4 % ) ;
;     -- Combinational with no register       ; 121                 ;
;     -- Register only                        ; 0                   ;
;     -- Combinational with a register        ; 56                  ;
;                                             ;                     ;
; Logic element usage by number of LUT inputs ;                     ;
;     -- 4 input functions                    ; 97                  ;
;     -- 3 input functions                    ; 24                  ;
;     -- <=2 input functions                  ; 56                  ;
;     -- Register only                        ; 0                   ;
;                                             ;                     ;
; Logic elements by mode                      ;                     ;
;     -- normal mode                          ; 136                 ;
;     -- arithmetic mode                      ; 41                  ;
;                                             ;                     ;
; Total registers*                            ; 56 / 5,010 ( 1 % )  ;
;     -- Dedicated logic registers            ; 56 / 4,608 ( 1 % )  ;
;     -- I/O registers                        ; 0 / 402 ( 0 % )     ;
;                                             ;                     ;
; Total LABs:  partially or completely used   ; 13 / 288 ( 5 % )    ;
; User inserted logic elements                ; 0                   ;
; Virtual pins                                ; 0                   ;
; I/O pins                                    ; 18 / 142 ( 13 % )   ;
;     -- Clock pins                           ; 1 / 4 ( 25 % )      ;
; Global signals                              ; 4                   ;
; M4Ks                                        ; 0 / 26 ( 0 % )      ;
; Total memory bits                           ; 0 / 119,808 ( 0 % ) ;
; Total RAM block bits                        ; 0 / 119,808 ( 0 % ) ;
; Embedded Multiplier 9-bit elements          ; 0 / 26 ( 0 % )      ;
; PLLs                                        ; 0 / 2 ( 0 % )       ;
; Global clocks                               ; 4 / 8 ( 50 % )      ;
; Average interconnect usage                  ; 0%                  ;
; Peak interconnect usage                     ; 1%                  ;
; Maximum fan-out node                        ; clock:inst|cnt[0]   ;
; Maximum fan-out                             ; 19                  ;
; Highest non-global fan-out signal           ; clock:inst|cnt[0]   ;
; Highest non-global fan-out                  ; 19                  ;
; Total fan-out                               ; 729                 ;
; Average fan-out                             ; 2.83                ;
+---------------------------------------------+---------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk  ; 23    ; 1        ; 0            ; 6            ; 0           ; 2                     ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
; key1 ; 96    ; 4        ; 24           ; 0            ; 2           ; 4                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
; key2 ; 95    ; 4        ; 21           ; 0            ; 0           ; 5                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
; key3 ; 99    ; 4        ; 24           ; 0            ; 0           ; 2                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
; key4 ; 97    ; 4        ; 24           ; 0            ; 1           ; 2                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                   ;
+--------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name         ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+--------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; 78ledcom[0]  ; 137   ; 3        ; 28           ; 9            ; 1           ; no              ; no                     ; no            ; no              ; no         ; no            ; no       ; Off          ; 3.3-V LVTTL  ; 24mA             ; Off         ; User                 ; 0 pF ;