?? jsai.tan.rpt
字號:
Timing Analyzer report for jsai
Thu May 01 10:44:52 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'SysClk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+-----------+-----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-----------+-----------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 17.870 ns ; count[2] ; SCAN[0] ; SysClk ; -- ; 0 ;
; Clock Setup: 'SysClk' ; N/A ; None ; 267.59 MHz ( period = 3.737 ns ) ; fcount[1] ; fcount[4] ; SysClk ; SysClk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+-----------+-----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; SysClk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'SysClk' ;
+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 267.59 MHz ( period = 3.737 ns ) ; fcount[1] ; fcount[4] ; SysClk ; SysClk ; None ; None ; 3.476 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[1] ; fcount[6] ; SysClk ; SysClk ; None ; None ; 3.271 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[1] ; fcount[3] ; SysClk ; SysClk ; None ; None ; 3.234 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[6] ; fcount[4] ; SysClk ; SysClk ; None ; None ; 3.138 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[1] ; fcount[7] ; SysClk ; SysClk ; None ; None ; 3.103 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[1] ; fcount[5] ; SysClk ; SysClk ; None ; None ; 3.097 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[2] ; fcount[4] ; SysClk ; SysClk ; None ; None ; 3.065 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[2] ; fcount[6] ; SysClk ; SysClk ; None ; None ; 3.027 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[0] ; fcount[4] ; SysClk ; SysClk ; None ; None ; 2.987 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[2] ; fcount[3] ; SysClk ; SysClk ; None ; None ; 2.986 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[0] ; fcount[6] ; SysClk ; SysClk ; None ; None ; 2.962 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[3] ; fcount[6] ; SysClk ; SysClk ; None ; None ; 2.943 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[0] ; fcount[3] ; SysClk ; SysClk ; None ; None ; 2.925 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[5] ; fcount[6] ; SysClk ; SysClk ; None ; None ; 2.925 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[2] ; fcount[7] ; SysClk ; SysClk ; None ; None ; 2.859 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[4] ; fcount[6] ; SysClk ; SysClk ; None ; None ; 2.859 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[2] ; fcount[5] ; SysClk ; SysClk ; None ; None ; 2.853 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[5] ; fcount[7] ; SysClk ; SysClk ; None ; None ; 2.837 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[0] ; fcount[7] ; SysClk ; SysClk ; None ; None ; 2.794 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[0] ; fcount[5] ; SysClk ; SysClk ; None ; None ; 2.788 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[3] ; fcount[7] ; SysClk ; SysClk ; None ; None ; 2.775 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[3] ; fcount[5] ; SysClk ; SysClk ; None ; None ; 2.769 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[1] ; fcount[2] ; SysClk ; SysClk ; None ; None ; 2.758 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[4] ; fcount[7] ; SysClk ; SysClk ; None ; None ; 2.691 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[3] ; fcount[4] ; SysClk ; SysClk ; None ; None ; 2.686 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[4] ; fcount[5] ; SysClk ; SysClk ; None ; None ; 2.685 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[6] ; fcount[7] ; SysClk ; SysClk ; None ; None ; 2.602 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[0] ; fcount[1] ; SysClk ; SysClk ; None ; None ; 2.558 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[0] ; fcount[2] ; SysClk ; SysClk ; None ; None ; 2.449 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[5] ; fcount[4] ; SysClk ; SysClk ; None ; None ; 2.402 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[7] ; fcount[4] ; SysClk ; SysClk ; None ; None ; 2.398 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[3] ; fcount[3] ; SysClk ; SysClk ; None ; None ; 2.382 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[1] ; q1 ; SysClk ; SysClk ; None ; None ; 2.357 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[1] ; fcount[1] ; SysClk ; SysClk ; None ; None ; 2.354 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[6] ; fcount[6] ; SysClk ; SysClk ; None ; None ; 2.172 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[5] ; fcount[5] ; SysClk ; SysClk ; None ; None ; 2.158 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[4] ; fcount[4] ; SysClk ; SysClk ; None ; None ; 2.135 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; fcount[6] ; q1 ; SysClk ; SysClk ; None ; None ; 2.040 ns ;
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