?? jk_ff.tan.qmsg
字號:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "C register QN~reg0 register Q~reg0 175.44 MHz 5.7 ns Internal " "Info: Clock \"C\" has Internal fmax of 175.44 MHz between source register \"QN~reg0\" and destination register \"Q~reg0\" (period= 5.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns QN~reg0 1 REG LC1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 3; REG Node = 'QN~reg0'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "" { QN~reg0 } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 17 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns Q~reg0 2 REG LC2 3 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC2; Fanout = 3; REG Node = 'Q~reg0'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "3.600 ns" { QN~reg0 Q~reg0 } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 17 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" { } { } 0} } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "3.600 ns" { QN~reg0 Q~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { QN~reg0 Q~reg0 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "C destination 1.300 ns + Shortest register " "Info: + Shortest clock path from clock \"C\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns C 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'C'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "" { C } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns Q~reg0 2 REG LC2 3 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC2; Fanout = 3; REG Node = 'Q~reg0'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "0.100 ns" { C Q~reg0 } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 17 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "1.300 ns" { C Q~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { C C~out Q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "C source 1.300 ns - Longest register " "Info: - Longest clock path from clock \"C\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns C 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'C'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "" { C } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns QN~reg0 2 REG LC1 3 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 3; REG Node = 'QN~reg0'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "0.100 ns" { C QN~reg0 } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 17 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "1.300 ns" { C QN~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { C C~out QN~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "1.300 ns" { C Q~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { C C~out Q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "1.300 ns" { C QN~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { C C~out QN~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" { } { { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 17 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" { } { { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 17 -1 0 } } } 0} } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "3.600 ns" { QN~reg0 Q~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { QN~reg0 Q~reg0 } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "1.300 ns" { C Q~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { C C~out Q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "1.300 ns" { C QN~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { C C~out QN~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "QN~reg0 K C 3.300 ns register " "Info: tsu for register \"QN~reg0\" (data pin = \"K\", clock pin = \"C\") is 3.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns + Longest pin register " "Info: + Longest pin to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns K 1 PIN PIN_21 4 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_21; Fanout = 4; PIN Node = 'K'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "" { K } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.800 ns QN~reg0 2 REG LC1 3 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC1; Fanout = 3; REG Node = 'QN~reg0'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "3.600 ns" { K QN~reg0 } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 17 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 73.68 % " "Info: Total cell delay = 2.800 ns ( 73.68 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 26.32 % " "Info: Total interconnect delay = 1.000 ns ( 26.32 % )" { } { } 0} } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "3.800 ns" { K QN~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { K K~out QN~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" { } { { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 17 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "C destination 1.300 ns - Shortest register " "Info: - Shortest clock path from clock \"C\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns C 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'C'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "" { C } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns QN~reg0 2 REG LC1 3 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 3; REG Node = 'QN~reg0'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "0.100 ns" { C QN~reg0 } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 17 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "1.300 ns" { C QN~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { C C~out QN~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "3.800 ns" { K QN~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { K K~out QN~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } } { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "1.300 ns" { C QN~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { C C~out QN~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "C Q Q~reg0 2.800 ns register " "Info: tco from clock \"C\" to destination pin \"Q\" through register \"Q~reg0\" is 2.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "C source 1.300 ns + Longest register " "Info: + Longest clock path from clock \"C\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns C 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'C'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "" { C } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns Q~reg0 2 REG LC2 3 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC2; Fanout = 3; REG Node = 'Q~reg0'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "0.100 ns" { C Q~reg0 } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 17 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "1.300 ns" { C Q~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { C C~out Q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" { } { { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 17 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.200 ns + Longest register pin " "Info: + Longest register to pin delay is 0.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q~reg0 1 REG LC2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 3; REG Node = 'Q~reg0'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "" { Q~reg0 } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 17 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Q 2 PIN PIN_5 0 " "Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'Q'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "0.200 ns" { Q~reg0 Q } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 4 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.200 ns 100.00 % " "Info: Total cell delay = 0.200 ns ( 100.00 % )" { } { } 0} } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "0.200 ns" { Q~reg0 Q } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { Q~reg0 Q } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } } } 0} } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "1.300 ns" { C Q~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { C C~out Q~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "0.200 ns" { Q~reg0 Q } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { Q~reg0 Q } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "QN~reg0 K C -0.800 ns register " "Info: th for register \"QN~reg0\" (data pin = \"K\", clock pin = \"C\") is -0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "C destination 1.300 ns + Longest register " "Info: + Longest clock path from clock \"C\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns C 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'C'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "" { C } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns QN~reg0 2 REG LC1 3 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 3; REG Node = 'QN~reg0'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "0.100 ns" { C QN~reg0 } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 17 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "1.300 ns" { C QN~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { C C~out QN~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.700 ns + " "Info: + Micro hold delay of destination is 1.700 ns" { } { { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 17 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns K 1 PIN PIN_21 4 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_21; Fanout = 4; PIN Node = 'K'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "" { K } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.800 ns QN~reg0 2 REG LC1 3 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC1; Fanout = 3; REG Node = 'QN~reg0'" { } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "3.600 ns" { K QN~reg0 } "NODE_NAME" } "" } } { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代碼/第2章/JK_FF/JK_FF.v" 17 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 73.68 % " "Info: Total cell delay = 2.800 ns ( 73.68 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 26.32 % " "Info: Total interconnect delay = 1.000 ns ( 26.32 % )" { } { } 0} } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "3.800 ns" { K QN~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { K K~out QN~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } } } 0} } { { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "1.300 ns" { C QN~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { C C~out QN~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" "" { Report "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF_cmp.qrpt" Compiler "JK_FF" "UNKNOWN" "V1" "D:/戴仙金/verilog/源代碼/第2章/JK_FF/db/JK_FF.quartus_db" { Floorplan "D:/戴仙金/verilog/源代碼/第2章/JK_FF/" "" "3.800 ns" { K QN~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { K K~out QN~reg0 } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 08 20:39:13 2006 " "Info: Processing ended: Tue Aug 08 20:39:13 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0} } { } 0}
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