?? complex_add.mdl
字號:
$ObjectID 10
Array {
Type "Cell"
Dimension 12
Cell "IncludeMdlTerminateFcn"
Cell "CombineOutputUpdateFcns"
Cell "SuppressErrorStatus"
Cell "ERTCustomFileBanners"
Cell "GenerateSampleERTMain"
Cell "MultiInstanceERTCode"
Cell "PurelyIntegerCode"
Cell "SupportNonFinite"
Cell "SupportComplex"
Cell "SupportAbsoluteTime"
Cell "SupportContinuousTime"
Cell "SupportNonInlinedSFcns"
PropName "DisabledProps"
}
Version "1.1.0"
TargetFcnLib "ansi_tfl_tmw.mat"
TargetLibSuffix ""
TargetPreCompLibLocation ""
GenFloatMathFcnCalls "ANSI_C"
UtilityFuncGeneration "Auto"
GenerateFullHeader on
GenerateSampleERTMain off
IsPILTarget off
ModelReferenceCompliant on
IncludeMdlTerminateFcn on
CombineOutputUpdateFcns off
SuppressErrorStatus off
IncludeFileDelimiter "Auto"
ERTCustomFileBanners off
SupportAbsoluteTime on
LogVarNameModifier "rt_"
MatFileLogging on
MultiInstanceERTCode off
SupportNonFinite on
SupportComplex on
PurelyIntegerCode off
SupportContinuousTime on
SupportNonInlinedSFcns on
ExtMode off
ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
GenerateASAP2 off
}
PropName "Components"
}
}
PropName "Components"
}
Name "Configuration"
SimulationMode "normal"
CurrentDlgPage "Solver"
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 1
}
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType DiscretePulseGenerator
PulseType "Sample based"
TimeSource "Use simulation time"
Amplitude "1"
Period "2"
PulseWidth "1"
PhaseDelay "0"
SampleTime "1"
VectorParams1D on
}
Block {
BlockType Scope
Floating off
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "0"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Terminator
}
Block {
BlockType UniformRandomNumber
Minimum "-1"
Maximum "1"
Seed "0"
SampleTime "-1"
VectorParams1D on
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "complex_add"
Location [133, 119, 920, 730]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name " System Generator"
Tag "genX"
Ports []
Position [52, 18, 103, 68]
ShowName off
AttributesFormatString "System\\nGenerator"
UserDataPersistent on
UserData "DataTag0"
SourceBlock "xbsIndex_r4/ System Generator"
SourceType "Xilinx System Generator"
ShowPortLabels on
xilinxfamily "Virtex2"
part "xc2v40"
speed "-4"
package "cs144"
synthesis_tool "XST"
directory "./netlist"
testbench off
simulink_period "1"
sysclk_period "100"
incr_netlist off
trim_vbits "Everywhere in SubSystem"
dbl_ovrd "According to Block Masks"
core_generation "According to Block Masks"
run_coregen off
deprecated_control off
eval_field "0"
block_type "sysgen"
}
Block {
BlockType Reference
Name "AddSub"
Ports [2, 1]
Position [380, 182, 430, 233]
SourceBlock "xbsIndex_r4/AddSub"
SourceType "Xilinx Adder/Subtractor Block"
mode "Addition"
use_carryin off
use_carryout off
en off
latency "0"
precision "User Defined"
arith_type "Unsigned"
n_bits "8"
bin_pt "5"
quantization "Truncate"
overflow "Wrap"
dbl_ovrd off
use_behavioral_HDL on
pipelined off
use_rpm on
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "addsub"
sg_icon_stat "50,51,2,1,white,blue,0,84d1e665"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 "
"32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 "
"38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 0 50 50 0 ],[0 51 51 0"
" 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: beg"
"in icon text ');\ncolor('black');port_label('input',1,'a');\ncolor('black');p"
"ort_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'"
",'texmode','on');\nfprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "AddSub1"
Ports [2, 1]
Position [380, 372, 430, 423]
SourceBlock "xbsIndex_r4/AddSub"
SourceType "Xilinx Adder/Subtractor Block"
mode "Addition"
use_carryin off
use_carryout off
en off
latency "0"
precision "User Defined"
arith_type "Unsigned"
n_bits "8"
bin_pt "5"
quantization "Truncate"
overflow "Wrap"
dbl_ovrd off
use_behavioral_HDL on
pipelined off
use_rpm on
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "addsub"
sg_icon_stat "50,51,2,1,white,blue,0,84d1e665"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 50 50 0 ],[0 0 51 51 ],[0.77 0.82 0.91]);\npatch([11 3 15 3 11 24 28 "
"32 46 35 24 16 28 16 24 35 46 32 28 24 11 ],[6 14 26 38 46 46 42 46 46 35 46 "
"38 26 14 6 17 6 6 10 6 6 ],[0.98 0.96 0.92]);\nplot([0 0 50 50 0 ],[0 51 51 0"
" 0 ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: beg"
"in icon text ');\ncolor('black');port_label('input',1,'a');\ncolor('black');p"
"ort_label('input',2,'b');\ncolor('black');port_label('output',1,'\\bf{a + b}'"
",'texmode','on');\nfprintf('','COMMENT: end icon text');\n"
}
Block {
BlockType Reference
Name "Gateway In"
Ports [1, 1]
Position [200, 164, 255, 186]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simu"
"link integer, double and fixed point to Xilinx fixed point type.<P><P>Hardwa"
"re notes: In hardware these blocks become top level input ports."
arith_type "Signed (2's comp)"
n_bits "8"
bin_pt "6"
quantization "Truncate"
overflow "Wrap"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "gatewayin"
sg_icon_stat "55,22,1,1,white,yellow,0,4bb76ffd"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In "
"','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','C"
"OMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this lin"
"e -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "Gateway In1"
Ports [1, 1]
Position [200, 234, 255, 256]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simu"
"link integer, double and fixed point to Xilinx fixed point type.<P><P>Hardwa"
"re notes: In hardware these blocks become top level input ports."
arith_type "Signed (2's comp)"
n_bits "8"
bin_pt "6"
quantization "Truncate"
overflow "Wrap"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "gatewayin"
sg_icon_stat "55,22,1,1,white,yellow,0,4bb76ffd"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In "
"','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','C"
"OMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this lin"
"e -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "Gateway In2"
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