?? complex_add.mdl
字號:
Ports [1, 1]
Position [200, 349, 255, 371]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simu"
"link integer, double and fixed point to Xilinx fixed point type.<P><P>Hardwa"
"re notes: In hardware these blocks become top level input ports."
arith_type "Signed (2's comp)"
n_bits "8"
bin_pt "6"
quantization "Truncate"
overflow "Wrap"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "gatewayin"
sg_icon_stat "55,22,1,1,white,yellow,0,4bb76ffd"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In "
"','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','C"
"OMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this lin"
"e -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "Gateway In3"
Ports [1, 1]
Position [200, 419, 255, 441]
SourceBlock "xbsIndex_r4/Gateway In"
SourceType "Xilinx Gateway In Block"
infoedit "Gateway in block. Converts inputs of type Simu"
"link integer, double and fixed point to Xilinx fixed point type.<P><P>Hardwa"
"re notes: In hardware these blocks become top level input ports."
arith_type "Signed (2's comp)"
n_bits "8"
bin_pt "6"
quantization "Truncate"
overflow "Wrap"
period "1"
dbl_ovrd off
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "gatewayin"
sg_icon_stat "55,22,1,1,white,yellow,0,4bb76ffd"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,'\\fontsize{11pt}\\bf In "
"','texmode','on');\ncolor('black');port_label('output',1,' ');\nfprintf('','C"
"OMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this lin"
"e -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "Gateway Out"
Ports [1, 1]
Position [495, 199, 550, 221]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed point"
" inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Ha"
"rdware notes: In hardware these blocks become top level output ports or are "
"discarded, depending on how they are configured."
hdl_port on
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "gatewayout"
sg_icon_stat "55,22,1,1,white,yellow,0,f0cec300"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,' ');\ncolor('black');por"
"t_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','"
"COMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this li"
"ne -- machine generated code. ');\n"
}
Block {
BlockType Reference
Name "Gateway Out1"
Ports [1, 1]
Position [495, 389, 550, 411]
SourceBlock "xbsIndex_r4/Gateway Out"
SourceType "Xilinx Gateway Out Block"
infoedit "Gateway out block. Converts Xilinx fixed point"
" inputs into ouputs of type Simulink integer, double, or fixed point.<P><P>Ha"
"rdware notes: In hardware these blocks become top level output ports or are "
"discarded, depending on how they are configured."
hdl_port on
timing_constraint "None"
locs_specified off
LOCs "{}"
xl_use_area off
xl_area "[0, 0, 0, 0, 0, 0, 0]"
block_version "VER_STRING_GOES_HERE"
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "gatewayout"
sg_icon_stat "55,22,1,1,white,yellow,0,f0cec300"
sg_mask_display "fprintf('','COMMENT: begin icon graphics ');\np"
"atch([0 55 55 0 ],[0 0 22 22 ],[0.95 0.93 0.65]);\npatch([22 18 23 18 22 28 3"
"0 32 38 33 28 25 31 25 28 33 38 32 30 28 22 ],[2 6 11 16 20 20 18 20 20 15 20"
" 17 11 5 2 7 2 2 4 2 2 ],[0.98 0.96 0.92]);\nplot([0 0 55 55 0 ],[0 22 22 0 0"
" ]);\nfprintf('','COMMENT: end icon graphics');\n\nfprintf('','COMMENT: begin"
" icon text ');\ncolor('black');port_label('input',1,' ');\ncolor('black');por"
"t_label('output',1,'\\fontsize{11pt}\\bf Out ','texmode','on');\nfprintf('','"
"COMMENT: end icon text');\nfprintf('','COMMENT: Make no changes above this li"
"ne -- machine generated code. ');\n"
}
Block {
BlockType Scope
Name "Imaginary"
Ports [1]
Position [620, 384, 650, 416]
Location [188, 390, 512, 629]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
SaveName "ScopeData1"
DataFormat "StructureWithTime"
}
Block {
BlockType Scope
Name "Real"
Ports [1]
Position [615, 194, 645, 226]
Location [217, 115, 541, 354]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
DataFormat "StructureWithTime"
}
Block {
BlockType UniformRandomNumber
Name "a"
Position [135, 159, 165, 191]
SampleTime "0"
}
Block {
BlockType UniformRandomNumber
Name "b"
Position [135, 344, 165, 376]
Seed "2"
SampleTime "0"
}
Block {
BlockType UniformRandomNumber
Name "c"
Position [135, 229, 165, 261]
Seed "1"
SampleTime "0"
}
Block {
BlockType UniformRandomNumber
Name "d"
Position [135, 414, 165, 446]
Seed "3"
SampleTime "0"
}
Line {
SrcBlock "a"
SrcPort 1
DstBlock "Gateway In"
DstPort 1
}
Line {
SrcBlock "c"
SrcPort 1
DstBlock "Gateway In1"
DstPort 1
}
Line {
SrcBlock "b"
SrcPort 1
DstBlock "Gateway In2"
DstPort 1
}
Line {
SrcBlock "d"
SrcPort 1
DstBlock "Gateway In3"
DstPort 1
}
Line {
SrcBlock "Gateway In"
SrcPort 1
Points [50, 0; 0, 20]
DstBlock "AddSub"
DstPort 1
}
Line {
SrcBlock "Gateway In1"
SrcPort 1
Points [50, 0; 0, -25]
DstBlock "AddSub"
DstPort 2
}
Line {
SrcBlock "Gateway In2"
SrcPort 1
Points [50, 0; 0, 25]
DstBlock "AddSub1"
DstPort 1
}
Line {
SrcBlock "Gateway In3"
SrcPort 1
Points [50, 0; 0, -20]
DstBlock "AddSub1"
DstPort 2
}
Line {
SrcBlock "AddSub"
SrcPort 1
DstBlock "Gateway Out"
DstPort 1
}
Line {
SrcBlock "AddSub1"
SrcPort 1
DstBlock "Gateway Out1"
DstPort 1
}
Line {
SrcBlock "Gateway Out"
SrcPort 1
DstBlock "Real"
DstPort 1
}
Line {
SrcBlock "Gateway Out1"
SrcPort 1
DstBlock "Imaginary"
DstPort 1
}
}
}
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