Timing Analyzer report for topclock
Mon Apr 07 07:01:30 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. Clock Setup: 'setm'
  7. Clock Setup: 'seth'
  8. Clock Setup: 'setd'
  9. tsu
 10. tco
 11. tpd
 12. th
 13. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                              ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From              ; To                ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 8.523 ns                                       ; set               ; hour1:u3|comb~5   ; --         ; seth     ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 27.530 ns                                      ; day1:u4|day[0]    ; Day[0]            ; clk        ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 9.884 ns                                       ; reset             ; Alarm             ; --         ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; 11.717 ns                                      ; reset             ; hour1:u3|Enhour   ; --         ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 248.88 MHz ( period = 4.018 ns )               ; minute1:u2|min[0] ; minute1:u2|min[5] ; clk        ; clk      ; 0            ;
; Clock Setup: 'setm'          ; N/A   ; None          ; 249.94 MHz ( period = 4.001 ns )               ; minute1:u2|comb~1 ; minute1:u2|comb~6 ; setm       ; setm     ; 0            ;
; Clock Setup: 'seth'          ; N/A   ; None          ; 270.34 MHz ( period = 3.699 ns )               ; hour1:u3|comb~1   ; hour1:u3|comb~4   ; seth       ; seth     ; 0            ;
; Clock Setup: 'setd'          ; N/A   ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; day1:u4|comb~1    ; day1:u4|comb~1    ; setd       ; setd     ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                   ;                   ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+-------------------+-------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;