?? day1.vhd
字號(hào):
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity day1 is
Port(
clkd,set,reset:in std_logic;
setd:in std_logic; --――置數(shù)端(星期)
day:buffer std_logic_vector(2 downto 0)
); -- ――星期輸出端
end;
Architecture a of day1 is
Begin
Process(clkd,reset,set,setd)
variable d:std_logic_vector(2 downto 0);
Begin
If reset='0' then
day<="000"; -- ――對(duì)星期計(jì)時(shí)器清0
Elsif set='1' then
if rising_edge(setd) then --――對(duì)星期計(jì)時(shí)器置d1的數(shù)
if d=6 then
d:="000";
else
d:=d+1;
end if;
end if;
day<=d;
Elsif clkd'event and clkd='1' then
If day=6 then
day<="000"; --――重復(fù)計(jì)數(shù)
Else
day<=day+1;
End if;
End if;
End process;
End;
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