Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;

Entity second1 is
 Port(clk,reset:in std_logic;
      Sec:buffer std_logic_vector(7 downto 0);      -- ――秒輸出端
      Ensec:out std_logic		 --――秒計時器的進位，用來驅動分計時器
	 );             
End;

Architecture a of second1 is
Begin
 Process(clk,reset)
  Begin
   If reset='0' then
		sec<="00000000";          -- ――對秒計時器清0
   Elsif clk'event and clk='1' then
     if sec=59 then
		sec<="00000000";ensec<='1';    --――重復計數并產生進位   
     else 
		sec<=sec+1;ensec<='0';                               --以驅動下一級
     end if;
   end if;
End process;
End;