{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "hour1:u3\|Enhour " "Info: Detected ripple clock \"hour1:u3\|Enhour\" as buffer" {  } { { "hour1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/hour1.vhd" 10 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "hour1:u3\|Enhour" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "minute1:u2\|enmin " "Info: Detected ripple clock \"minute1:u2\|enmin\" as buffer" {  } { { "minute1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/minute1.vhd" 11 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "minute1:u2\|enmin" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "second1:u1\|Ensec " "Info: Detected ripple clock \"second1:u1\|Ensec\" as buffer" {  } { { "second1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/second1.vhd" 9 -1 0 } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "second1:u1\|Ensec" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register minute1:u2\|min\[0\] register minute1:u2\|min\[5\] 248.88 MHz 4.018 ns Internal " "Info: Clock \"clk\" has Internal fmax of 248.88 MHz between source register \"minute1:u2\|min\[0\]\" and destination register \"minute1:u2\|min\[5\]\" (period= 4.018 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.757 ns + Longest register register " "Info: + Longest register to register delay is 3.757 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns minute1:u2\|min\[0\] 1 REG LC_X12_Y7_N7 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y7_N7; Fanout = 10; REG Node = 'minute1:u2\|min\[0\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { minute1:u2|min[0] } "NODE_NAME" } } { "minute1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/minute1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.788 ns) + CELL(0.423 ns) 1.211 ns minute1:u2\|Add1~132 2 COMB LC_X13_Y7_N0 2 " "Info: 2: + IC(0.788 ns) + CELL(0.423 ns) = 1.211 ns; Loc. = LC_X13_Y7_N0; Fanout = 2; COMB Node = 'minute1:u2\|Add1~132'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.211 ns" { minute1:u2|min[0] minute1:u2|Add1~132 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.289 ns minute1:u2\|Add1~124 3 COMB LC_X13_Y7_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.289 ns; Loc. = LC_X13_Y7_N1; Fanout = 2; COMB Node = 'minute1:u2\|Add1~124'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { minute1:u2|Add1~132 minute1:u2|Add1~124 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.367 ns minute1:u2\|Add1~118 4 COMB LC_X13_Y7_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.367 ns; Loc. = LC_X13_Y7_N2; Fanout = 2; COMB Node = 'minute1:u2\|Add1~118'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { minute1:u2|Add1~124 minute1:u2|Add1~118 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.445 ns minute1:u2\|Add1~126 5 COMB LC_X13_Y7_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 1.445 ns; Loc. = LC_X13_Y7_N3; Fanout = 2; COMB Node = 'minute1:u2\|Add1~126'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { minute1:u2|Add1~118 minute1:u2|Add1~126 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.623 ns minute1:u2\|Add1~128 6 COMB LC_X13_Y7_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 1.623 ns; Loc. = LC_X13_Y7_N4; Fanout = 3; COMB Node = 'minute1:u2\|Add1~128'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.178 ns" { minute1:u2|Add1~126 minute1:u2|Add1~128 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.244 ns minute1:u2\|Add1~129 7 COMB LC_X13_Y7_N5 1 " "Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 2.244 ns; Loc. = LC_X13_Y7_N5; Fanout = 1; COMB Node = 'minute1:u2\|Add1~129'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.621 ns" { minute1:u2|Add1~128 minute1:u2|Add1~129 } "NODE_NAME" } } { "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/program files/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.292 ns) 3.266 ns minute1:u2\|min~181 8 COMB LC_X14_Y7_N3 1 " "Info: 8: + IC(0.730 ns) + CELL(0.292 ns) = 3.266 ns; Loc. = LC_X14_Y7_N3; Fanout = 1; COMB Node = 'minute1:u2\|min~181'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.022 ns" { minute1:u2|Add1~129 minute1:u2|min~181 } "NODE_NAME" } } { "minute1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/minute1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 3.757 ns minute1:u2\|min\[5\] 9 REG LC_X14_Y7_N4 6 " "Info: 9: + IC(0.182 ns) + CELL(0.309 ns) = 3.757 ns; Loc. = LC_X14_Y7_N4; Fanout = 6; REG Node = 'minute1:u2\|min\[5\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.491 ns" { minute1:u2|min~181 minute1:u2|min[5] } "NODE_NAME" } } { "minute1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/minute1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.057 ns ( 54.75 % ) " "Info: Total cell delay = 2.057 ns ( 54.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns ( 45.25 % ) " "Info: Total interconnect delay = 1.700 ns ( 45.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.757 ns" { minute1:u2|min[0] minute1:u2|Add1~132 minute1:u2|Add1~124 minute1:u2|Add1~118 minute1:u2|Add1~126 minute1:u2|Add1~128 minute1:u2|Add1~129 minute1:u2|min~181 minute1:u2|min[5] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.757 ns" { minute1:u2|min[0] minute1:u2|Add1~132 minute1:u2|Add1~124 minute1:u2|Add1~118 minute1:u2|Add1~126 minute1:u2|Add1~128 minute1:u2|Add1~129 minute1:u2|min~181 minute1:u2|min[5] } { 0.000ns 0.788ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.730ns 0.182ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.621ns 0.292ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.973 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 12.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_180 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "topclock.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/topclock.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.538 ns) + CELL(0.935 ns) 7.942 ns second1:u1\|Ensec 2 REG LC_X6_Y9_N6 9 " "Info: 2: + IC(5.538 ns) + CELL(0.935 ns) = 7.942 ns; Loc. = LC_X6_Y9_N6; Fanout = 9; REG Node = 'second1:u1\|Ensec'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.473 ns" { clk second1:u1|Ensec } "NODE_NAME" } } { "second1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/second1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.320 ns) + CELL(0.711 ns) 12.973 ns minute1:u2\|min\[5\] 3 REG LC_X14_Y7_N4 6 " "Info: 3: + IC(4.320 ns) + CELL(0.711 ns) = 12.973 ns; Loc. = LC_X14_Y7_N4; Fanout = 6; REG Node = 'minute1:u2\|min\[5\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.031 ns" { second1:u1|Ensec minute1:u2|min[5] } "NODE_NAME" } } { "minute1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/minute1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 24.01 % ) " "Info: Total cell delay = 3.115 ns ( 24.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.858 ns ( 75.99 % ) " "Info: Total interconnect delay = 9.858 ns ( 75.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.973 ns" { clk second1:u1|Ensec minute1:u2|min[5] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "12.973 ns" { clk clk~out0 second1:u1|Ensec minute1:u2|min[5] } { 0.000ns 0.000ns 5.538ns 4.320ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.973 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_180 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_180; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "topclock.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/topclock.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.538 ns) + CELL(0.935 ns) 7.942 ns second1:u1\|Ensec 2 REG LC_X6_Y9_N6 9 " "Info: 2: + IC(5.538 ns) + CELL(0.935 ns) = 7.942 ns; Loc. = LC_X6_Y9_N6; Fanout = 9; REG Node = 'second1:u1\|Ensec'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.473 ns" { clk second1:u1|Ensec } "NODE_NAME" } } { "second1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/second1.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.320 ns) + CELL(0.711 ns) 12.973 ns minute1:u2\|min\[0\] 3 REG LC_X12_Y7_N7 10 " "Info: 3: + IC(4.320 ns) + CELL(0.711 ns) = 12.973 ns; Loc. = LC_X12_Y7_N7; Fanout = 10; REG Node = 'minute1:u2\|min\[0\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.031 ns" { second1:u1|Ensec minute1:u2|min[0] } "NODE_NAME" } } { "minute1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/minute1.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 24.01 % ) " "Info: Total cell delay = 3.115 ns ( 24.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.858 ns ( 75.99 % ) " "Info: Total interconnect delay = 9.858 ns ( 75.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.973 ns" { clk second1:u1|Ensec minute1:u2|min[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "12.973 ns" { clk clk~out0 second1:u1|Ensec minute1:u2|min[0] } { 0.000ns 0.000ns 5.538ns 4.320ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.973 ns" { clk second1:u1|Ensec minute1:u2|min[5] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "12.973 ns" { clk clk~out0 second1:u1|Ensec minute1:u2|min[5] } { 0.000ns 0.000ns 5.538ns 4.320ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.973 ns" { clk second1:u1|Ensec minute1:u2|min[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "12.973 ns" { clk clk~out0 second1:u1|Ensec minute1:u2|min[0] } { 0.000ns 0.000ns 5.538ns 4.320ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "minute1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/minute1.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "minute1.vhd" "" { Text "C:/Documents and Settings/Administrator.ZHONGNAN-A8BD31/桌面/topclock/minute1.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.757 ns" { minute1:u2|min[0] minute1:u2|Add1~132 minute1:u2|Add1~124 minute1:u2|Add1~118 minute1:u2|Add1~126 minute1:u2|Add1~128 minute1:u2|Add1~129 minute1:u2|min~181 minute1:u2|min[5] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.757 ns" { minute1:u2|min[0] minute1:u2|Add1~132 minute1:u2|Add1~124 minute1:u2|Add1~118 minute1:u2|Add1~126 minute1:u2|Add1~128 minute1:u2|Add1~129 minute1:u2|min~181 minute1:u2|min[5] } { 0.000ns 0.788ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.730ns 0.182ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.078ns 0.178ns 0.621ns 0.292ns 0.309ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.973 ns" { clk second1:u1|Ensec minute1:u2|min[5] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "12.973 ns" { clk clk~out0 second1:u1|Ensec minute1:u2|min[5] } { 0.000ns 0.000ns 5.538ns 4.320ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.973 ns" { clk second1:u1|Ensec minute1:u2|min[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "12.973 ns" { clk clk~out0 second1:u1|Ensec minute1:u2|min[0] } { 0.000ns 0.000ns 5.538ns 4.320ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}